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ISP1506A Datasheet(PDF) 8 Page - NXP Semiconductors |
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ISP1506A Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 80 page  ISP1506A_ISP1506B_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 28 August 2008 7 of 79 NXP Semiconductors ISP1506A; ISP1506B ULPI HS USB OTG transceiver 7. Functional description 7.1 ULPI interface controller The ISP1506 provides an 8-pin interface that is compliant with Ref. 3 “UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1”. This interface must be connected to the USB link. The ULPI interface controller provides the following functions: • ULPI compliant and register set • Allows full control over the USB peripheral, host and OTG functionality • Parses the USB transmit and receive data • Prioritizes the USB receive data, USB transmit data, interrupts and register operations • Control of the VBUS charge pump or external source • VBUS monitoring, charging and discharging • Low-power mode • 3-pin serial mode • Generates RXCMDs (status updates) • Maskable interrupts • Control over the ULPI bus state; can attach weak pull-down resistors to DATA[3:0] For more information on the ULPI protocol, see Section 9. 7.2 USB data serializer and deserializer The USB data serializer prepares data to transmit on the USB bus. To transmit data, the USB link sends a transmit command and data on the ULPI bus. The serializer performs parallel-to-serial conversion, bit stuffing and NRZI encoding. For packets with a PID, the serializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the end of the packet. When the serializer is busy and cannot accept any more data, the ULPI interface controller deasserts NXT. The USB data deserializer decodes data received from the USB bus. When data is received, the deserializer strips the SYNC and EOP patterns, and then performs serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data payload. The ULPI interface controller sends data to the USB link by asserting DIR, and then asserting NXT whenever a byte is ready. The deserializer also detects various receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and byte-alignment errors. 7.3 Hi-Speed USB (USB 2.0) ATX The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to transmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, for USB peripheral, host and OTG implementations. The following circuitry is included: • Differential drivers to transmit data at high-speed, full-speed and low-speed • Differential and single-ended receivers to receive data at high-speed, full-speed and low-speed |
Similar Part No. - ISP1506A_08 |
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Similar Description - ISP1506A_08 |
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