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HEF4094BT Datasheet(PDF) 3 Page - NXP Semiconductors |
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HEF4094BT Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 17 page HEF4094B_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 30 October 2008 3 of 17 NXP Semiconductors HEF4094B 8-stage shift-and-store bus register 5. Pinning information 5.1 Pinning 5.2 Pin description 6. Functional description Fig 4. Pin configuration HEF4094B STR VDD DOE CP QP4 QP0 QP5 QP1 QP6 QP2 QP7 QP3 QS2 VSS QS1 001aae662 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 Table 2. Pin description Symbol Pin Description STR 1 strobe input D 2 data input CP 3 clock input QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output VSS 8 ground supply voltage QS1 9 serial output QS2 10 serial output OE 15 output enable input VDD 16 supply voltage Table 3. Function table[1] Inputs Parallel outputs Serial outputs CP OE STR D QP0 QPn QS1 QS2 ↑ L X X Z Z Q6S NC ↓ L X X Z Z NC Q7S ↑ H L X NC NC QS6 NC ↑ H H L L QPn −1 QS6 NC ↑ HHHHQPn −1 QS6 NC |
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