HEF4044BT datasheet(6/13 Pages) NXP

Part #	HEF4044BT

Description	Quad R/S latch with 3-state outputs

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Manufacturer	NXP [NXP Semiconductors]

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HEF4044B_6

Product data sheet

Rev. 06 — 11 November 2008

6 of 13

NXP Semiconductors

HEF4044B

Quad R/S latch with 3-state outputs

12. Waveforms

Table 8.

Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.

Symbol

Parameter

VDD

Typical formula for PD (µW)

where:

PD

dynamic power

dissipation

5 V

PD = 1300 × fi + Σ(fo × CL) × VDD2

fi = input frequency in MHz,

fo = output frequency in MHz,

CL = output load capacitance in pF,

VDD = supply voltage in V,

Σ(C

L × fo) = sum of the outputs.

10 V

PD = 5200 × fi + Σ(fo × CL) × VDD2

15 V

PD = 12900 × fi + Σ(fo × CL) × VDD2

measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig 4.

Set (nS) and reset (nR) inputs pulse width and propagation delay to latch output (nQ) and

output nQ transition time

001aai543

output nQ

input nS

tTHL

tTLH

VOL

VOH

VM

VI

0 V

tr

tf

tW

90 %

10 %

input nR

VI

0 V

10 %

90 %

tPLH

tPHL

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