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SPC5704CEVMG Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc

Part # SPC5704CEVMG
Description  Microcontroller
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

SPC5704CEVMG Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc

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MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Overview
Freescale Semiconductor
6
Two full CAN 2.0B controllers with 64 configurable buffers each; the bit rate can be programmed up to 1 Mb/s
Up to four Inter-integrated circuit (I2C) internal bus controllers with master/slave bus interface
Up to 132 configurable general purpose pins supporting input and output operations
Real Time Counter (RTC). Clock sources are:
— Internal 128 kHz or 16 MHz RC oscillator supporting autonomous wake-up with 1 ms resolution with maximum
timeout of 2 seconds
— External 32 kHz crystal oscillator, supporting wake-up with 1 s resolution and maximum timeout of one hour
— External 4 - 16 MHz oscillator
System Timers:
— 4-channel 32-bit System Timer Module (STM)—included in processor platform
— 4-channel 32-bit Periodic Interrupt Timer (PIT) module
— System watchdog timer
System Integration Unit (SIU) module to manage resets, external interrupts, GPIO and pad control
System Status and Configuration Module (SSCM) to provide information for identification of the device, last boot
mode, or debug status and provides an entry point for the censorship password mechanism
Clock Generation Module (CGM) to generate system clock sources and provide a unified register interface, enabling
access to all clock sources
Clock Monitor Unit (CMU) to monitor the integrity of the main crystal oscillator and the PLL and act as a frequency
meter, measuring the frequency of one clock source and comparing it to a reference clock
Mode Entry Module (MEM) to control the device power mode, i.e., RUN, HALT, STOP, or STANDBY, control mode
transition sequences, and manage the power control, voltage regulator, clock generation and clock management
modules
Reset Generation Module (RGM) to manage reset assertion and release to the device at initial power-up
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard
Device/board boundary-scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)
On-chip voltage regulator controller for regulating the 3.3 or 5 V supply voltage down to 1.2 V for core logic (requires
external ballast transistor)
The MPC5606S microcontrollers are offered in the following packages:1
— 144 LQFP, 0.5 mm pitch, 20 mm
× 20 mm outline
— 176 LQFP, 0.5 mm pitch, 24 mm
× 24 mm outline
— 208 MAPBGA, 1.0 mm pitch, 17 mm
× 17 mm outline
1.3
MPC5606S Series Blocks
1.3.1
Block Diagram
Figure 1 shows a top-level block diagram of the MPC5606S series.
1. See the device comparison table or orderable parts summary for package offerings for each device in the family.


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