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74LVT574BQ Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LVT574BQ Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 16 page 74LVT_LVTH574_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 September 2008 3 of 16 NXP Semiconductors 74LVT574; 74LVTH574 3.3 V octal D-type flip-flop; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input Fig 4. Pin configuration for SO20, and (T)SSOP20 Fig 5. Pin configuration for DHVQFN20 74LVT574 74LVTH574 OE VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND CP 001aae758 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 001aah711 74LVT574 74LVTH574 Transparent top view Q7 D6 D7 Q6 D5 Q5 D4 Q4 D3 Q3 D2 Q2 GND(1) D1 Q1 D0 Q0 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 terminal 1 index area Table 2. Pin description Symbol Pin Description OE 1 output enable input (active LOW) D0 to D7 2, 3, 4, 5, 6, 7, 8, 9 data input GND 10 ground (0 V) CP 11 clock pulse input (active rising edge) Q0 to Q7 19, 18, 17, 16, 15, 14, 13, 12 data output VCC 20 supply voltage |
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