CY25100
Document #: 38-07499 Rev. *F
Page 2 of 13
Pinouts
Figure 1. CY25100 8-Pin SOIC/TSSOP
General Description
The CY25100 is a Spread Spectrum Clock Generator (SSCG) IC
used to reduce EMI found in today’s high speed digital electronic
systems.
The device uses a Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy can significantly reduce the cost of complying with
regulatory
agency
(EMC)
requirements
and
improve
time-to-market without degrading system performance.
The CY25100 uses a factory or field-programmable configu-
ration memory array to synthesize output frequency, spread
percentage, crystal load capacitor, reference clock output on/off,
spread spectrum on/off function, and PD#/OE options.
The spread percentage is programmed to either center spread
or down spread with various spread percentages. The range for
center spread is from ±0.25% to ±2.50%. The range for down
spread is from –0.5% to –5.0%. Contact the factory for smaller
or larger spread percentage amounts, if required.
The input to the CY25100 can either be a crystal or a clock
signal. The input frequency range for crystals is 8 to 30 MHz, and
for clock signals is 8 to 166 MHz.
The CY25100 has two clock outputs, REFCLK and SSCLK. The
non spread spectrum REFCLK output has the same frequency
as the input of the CY25100. The frequency modulated SSCLK
output can be programmed from 3 to 200 MHz.
The CY25100 products are available in 8-pin SOIC and TSSOP
packages with commercial and industrial operating temperature
ranges.
Pin Description
Pin
Name
Description
1
VDD
3.3V power supply.
2
XOUT
Crystal output. Leave this pin floating if external clock is used.
3
XIN/CLKIN
Crystal input or reference clock input.
4
PD#/OE
Power down pin: Active LOW. If PD# = 0, PLL and Xtal are powered down, and outputs are
weakly pulled low.
Output Enable pin: Active HIGH. If OE = 1, SSCLK and REFCLK are enabled. User has the
option of choosing either PD# or OE function.
5
VSS
Power supply ground.
6
REFCLK
Buffered reference output.
7
SSCLK
Spread spectrum clock output.
8
SSON#
Spread spectrum control. 0 = spread on. 1 = spread off.
4
8
VDD
6
7
VSS
REFCLK
SSON#
1
2
3
XOUT
XIN/CLKIN
PD#/OE
SSCLK
5
Table 1.
Pin Function
Input
Frequency
Total Xtal
Load
Capacitance
Output
Frequency
Spread Percent
(0.5% – 5%,
0.25% Intervals)
Reference
Output
Power down or
Output Enable
Frequency
Modulation
Pin Name
XIN and XOUT XIN and XOUT
SSCLK
SSCLK
REFOUT
PD#/OE
SSCLK
Pin#
3 and 2
3 and 2
7
7
6
4
7
Unit
MHz
pF
MHz
%
On or Off
Select PD# or OE
kHz
Program Value
ENTER DATA
ENTER DATA ENTER DATA
ENTER DATA
ENTER DATA
ENTER DATA
31.5
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