CY25562
Document Number: 38-07392 Rev. *C
Page 2 of 8
General Description
CY25562 is a spread spectrum clock generator (SSCG) IC used
to reduce electromagnetic interference (EMI) found in today’s
high speed digital electronic systems.
CY25562 uses a Cypress proprietary Phase Locked Loop (PLL)
and Spread Spectrum Clock (SSC) technology to synthesize and
frequency modulate the input frequency of the reference clock.
By doing this, the measured EMI at the fundamental and
harmonic frequencies of clock (SSCLK) is greatly reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading system performance.
CY25562 is a very simple and versatile device to use. The
frequency and spread percentage range is selected by
programming S0 and S1 digital inputs. These inputs use three
logic states including high (H), low (L), and middle (M) logic
levels to select one of the nine available spread percentage
ranges. Refer to Table 1 for programming details.
CY25562 is intended for applications with a reference frequency
in the range of 50 to 200 MHz.
A wide range of digitally selectable spread percentages is made
possible by using tri-level (high, low, and middle) logic at the S0
and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
Spread spectrum clock control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
CY25562 is available in an eight-pin SOIC package with a 0 to
70°C operating temperature range.
Refer to CY25561 for applications with lower drive requirements,
and CY25560 with lower drive and frequency requirements.
Pinout
Figure 1. Pin Configuration
Pin Description
Pin #
Pin Name
Type
Pin Description
1
Xin/CLK
I
Clock or crystal connection input. Refer to Table 1 for input frequency range selection.
2
VDD
P
Positive power supply
3
GND
P
Power supply ground
4
SSCLK
O
SSCG modulated clock output
5
SSCC
I
Spread spectrum clock control (enable/disable) function. SSCG function is enabled when input
is high and disabled when input is low. This pin is pulled high internally.
6
S1
I
Tri-level logic input control pin used to select frequency and bandwidth. Frequency/bandwidth
selection and tri-level logic programming. See Figure 2. Pin 6 has internal resistor divider
network to VDD and VSS. Refer to Logic Block Diagram on page 1.
7
S0
I
Tri-level logic input control pin used to select frequency and bandwidth. Frequency/Bandwidth
selection and tri-level logic programming. See Figure 2. Pin 7 has internal resistor divider
network to VDD and VSS. Refer to Logic Block Diagram on page 1.
8
Xout
O
Oscillator output pin connected to crystal. Leave this pin unconnected If an external clock drives
Xin/CLK.
XIN/CLK
SSCLK
XOUT
CY25562
1
2
3
4
8
7
6
5
VDD
VSS
S0
S1
SSCC
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