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CY25561
Document Number: 38-07242 Rev. *C
Page 6 of 9
Part Number Application Schematic
Figure 4. Application Schematic
The schematic in Figure 4 above demonstrates how CY25561 is configured in a typical application. This application is using a 90 MHz
reference clock connected to pin 1. Because an external reference clock is used, pin 8 (XOUT) is left unconnected.
Figure 4 shows that pin 6 has no connection, which programs the logic “M” state, due to the internal resistor divider network of
CY25561. Programming a logic “0” state is as simple as connecting to logic ground, as shown on pin 7.
With this configuration, CY25561 produces an SSCG clock that is at a center frequency of 90 MHz. Referring to Table 3, range “M,
0” at 90 MHz generates a modulation profile that has a 3.1percent peak-to-peak spread.
VDD
1
SSCC
VSS
S1
S0
XIN/CLK
XOUT
SSCLK
VDD
CY25561
5
7
6
4
0.1 uF
C3
2
3
VDD
90 MHz Reference Clock
8
N/C = Logic "M" state
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