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CY5057
Document #: 38-07363 Rev. *E
Page 7 of 10
Switching Waveforms
Figure 2. Duty Cycle Timing (dc)
Figure 3. Output Rise/Fall Time
Figure 4. Power Down Timing (Synchronous and Asynchronous Modes)
Figure 5. Output Enable Timing (Synchronous and Asynchronous Modes)
t1A
t1B
Duty
t1A
t1B
--------
100%
[]
×
=
OUTPUT
OUTPUT
tr
VDD
0V
tf
High Impedance Weakly
Pulled Low
High Impedance
Weakly Pulled Low
VDD
POWER DOWN (PD#)
VIL
VIH
TSTP
TPU
CLKOUT
(synchronous)
CLKOUT
(asynchronous)
TSTP
TPU
High Impedance Weakly
Pulled Low
High Impedance
Weakly Pulled Low
VDD
OUTPUT ENABLE (OE)
CLKOUT
(synchronous)
CLKOUT
(asynchronous)
VIL
VIH
TPXZ
TPZX
TPXZ
TPZX
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