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CY2304
Document #: 38-07247 Rev. *E
Page 2 of 9
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Zero Delay and Skew Control
Figure 2. REF. Input to CLKA/CLKB Delay vs. Difference in Loading Between FBK Pin and CLKA/CLKB Pins
To close the feedback loop of the CY2304, the FBK pin can be driven from any of the four available output pins. The output driving
the FBK pin is driving a total load of 7 pF, with any additional load that it drives. The relative loading of this output (with respect to the
remaining outputs) can adjust the input-output delay. This is shown in Figure 2.
For applications requiring zero input-output delay, all outputs including the one providing feedback must be equally loaded. If
input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and
remaining outputs.
For zero output-output skew, be sure to load outputs equally. For further information on using CY2304, refer to the application note
AN1234 “CY2308: Zero Delay Buffer.”
Table 2. Pin Definitions - 8-Pin SOIC
Pin
Signal
Description
1
REF[1]
Input reference frequency, 5V tolerant input
2
CLKA1[2]
Clock output, Bank A
3
CLKA2[2]
Clock output, Bank A
4
GND
Ground
5
CLKB1[2]
Clock output, Bank B
6
CLKB2[2]
Clock output, Bank B
7VDD
3.3V supply
8
FBK
PLL feedback input
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
[+] Feedback
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