CY23S09, CY23S05
Document Number: 38-07296 Rev. *D
Page 4 of 9
Maximum Ratings
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage (Except REF) ............ –0.5V to VDD + 0.5V
DC Input Voltage REF
............................................. −0.5V to 7V
Storage Temperature ................................. –65
°C to +150°C
Maximum Soldering Temperature (10 seconds)......... 260
°C
Junction Temperature ................................................. 150
°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ........................... > 2,000V
Operating Conditions for CY23S05SC-XX and CY23S09SC-XX Commercial Temperature Devices[5]
Parameter
Description
Min
Max
Unit
VDD
Supply Voltage
3.0
3.6
V
TA
Operating Temperature (Ambient Temperature)
0
70
°C
CL
Load Capacitance, below 100 MHz
30
pF
CL
Load Capacitance, from 100 MHz to 133 MHz
10
pF
CIN
Input Capacitance
7
pF
Electrical Characteristics for CY23S05SC-XX and CY23S09SC-XX Commercial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
VIL
Input LOW Voltage[6]
0.8
V
VIH
Input HIGH Voltage[6]
2.0
V
IIL
Input LOW Current
VIN = 0V
50.0
μA
IIH
Input HIGH Current
VIN = VDD
100.0
μA
VOL
Output LOW Voltage[7]
IOL = 8 mA (–1)
IOH = 12 mA (–1H)
0.4
V
VOH
Output HIGH Voltage[7]
IOH = –8 mA (–1)
IOL = –12 mA (–1H)
2.4
V
IDD (PD mode)
Power Down Supply Current
REF = 0 MHz
12.0
μA
IDD
Supply Current
Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
32.0
mA
Switching Characteristics for CY23S05SC-1 and CY23S09SC-1 Commercial Temperature Devices [8]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
t1
Output Frequency
30 pF load
10 pF load
10
10
100
133.33
MHz
MHz
Duty Cycle[7] = t2 ÷ t1
Measured at 1.4V, Fout = 66.67 MHz
40.0
50.0
60.0
%
t3
Rise Time[7]
Measured between 0.8V and 2.0V
2.50
ns
t4
Fall Time[7]
Measured between 0.8V and 2.0V
2.50
ns
t5
Output-to-Output Skew[7]
All outputs equally loaded
250
ps
t6
Delay, REF Rising Edge to
CLKOUT Rising Edge[7]
Measured at VDD/2
0
±350
ps
t7
Device-to-Device Skew[7]
Measured at VDD/2 on the CLKOUT pins
of devices
0
700
ps
tJ
Cycle-to-Cycle Jitter[7]
Measured at 66.67 MHz, loaded outputs
200
ps
tLOCK
PLL Lock Time[7]
Stable power supply, valid clock
presented on REF pin
1.0
ms
Notes
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
6. REF input has a threshold voltage of VDD/2.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. All parameters specified with loaded outputs.
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