CY8CTMA120
Document Number: 001-46901 Rev. *C
Page 10 of 35
Figure 6. CY8CTMA120 OCD (Not for Production)
100-Pin Part Pinout (On-Chip Debug)
The 100-pin TQFP part is the CY8CTMA120 On-Chip Debug (OCD) TrueTouch device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 4. 100-Pin Part Pinout (TQFP)
Pin
No.
Name
Description
Pin
No.
Name
Description
1
NC
No connection. Leave floating.
51
IO
M
P1[6]
2
NC
No connection. Leave floating.
52
IO
M
P5[0]
3
IO
I, M P0[1]
Analog column mux input.
53
IO
M
P5[2]
4
IO
M
P2[7]
54
IO
M
P5[4]
5
IO
M
P2[5]
55
IO
M
P5[6]
6
IO
I, M P2[3]
Direct switched capacitor block input.
56
IO
M
P3[0]
7
IO
I, M P2[1]
Direct switched capacitor block input.
57
IO
M
P3[2]
8
IO
M
P4[7]
58
IO
M
P3[4]
9
IO
M
P4[5]
59
IO
M
P3[6]
10
IO
M
P4[3]
60
HCLK
OCD high speed clock output.
11
IO
M
P4[1]
61
CCLK
OCD CPU clock output.
12
OCDE OCD even data IO.
62
Input
XRES Active high pin reset with internal pull down.
13
OCDO OCD odd data output.
63
IO
M
P4[0]
14
NC
No connection. Leave floating.
64
IO
M
P4[2]
15
Power
Vss
Ground. Connect to circuit ground.
65
Power
Vss
Ground. Connect to circuit ground.
16
IO
M
P3[7]
66
IO
M
P4[4]
17
IO
M
P3[5]
67
IO
M
P4[6]
18
IO
M
P3[3]
68
IO
I, M
P2[0]
Direct switched capacitor block input.
19
IO
M
P3[1]
69
IO
I, M
P2[2]
Direct switched capacitor block input.
20
IO
M
P5[7]
70
IO
P2[4]
External Analog Ground (AGND) input.
21
IO
M
P5[5]
71
NC
No connection. Leave floating.
Pin
No.
Name
Description
Pin
No.
Name
Description
22
IO
M
P5[3]
72
IO
P2[6]
External Voltage Reference (VREF) input.
23
IO
M
P5[1]
73
NC
No connection. Leave floating.
24
IO
M
P1[7]
I2C Serial Clock (SCL).
74
IO
I
P0[0]
Analog column mux input.
25
NC
No connection. Leave floating.
75
NC
No connection. Leave floating.
Vss
Vss
NC
NC
NC
Vdd
NC
NC
Vss
Vss
Vss
Vss
P2[1]
P0[1]
P0[7]
Vdd
P0[2] P2[2]
Vss
Vss
NC
P4[1] P4[7]
P2[7]
P0[5] P0[6]
P0[0] P2[0]
P4[2]
NC
NC
P3[7] P4[5]
P2[5]
P0[3] P0[4]
P2[6] P4[6]
P4[0]
NC
NC
NC
P4[3]
P2[3]
Vss
Vss
P2[4] P4[4]
P3[6]
NC
NC
P5[7] P3[5]
P5[1]
Vss
Vss
P5[0] P3[0]
XRES
P7[1]
NC
P5[5] P3[3]
P1[7]
P1[1] P1[0]
P1[6] P3[4]
P5[6] P7[2]
NC
P5[3] P3[1]
P1[5]
P1[3] P1[2]
P1[4] P3[2]
P5[4] P7[3]
Vss
Vss
D +
D -
Vdd
P7[7]
P7[0] P5[2]
Vss
Vss
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5] P7[4]
Vss
Vss
1
2
34
56
78
9
10
A
B
C
D
E
F
G
H
J
K
BGA (Top View)
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