CY8C21123, CY8C21223, CY8C21323
PSoC® Mixed Signal Array
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document Number: 38-12022 Rev. *H
Revised October 22, 2008
Features
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Low power at High Speed
❐ 2.4V to 5.25V Operating Voltage
❐ Operating Voltages down to 1.0V using On-Chip Switch
Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■ Advanced Peripherals (PSoC Blocks)
❐ Four Analog Type “E” PSoC Blocks Provide:
• Two Comparators with DAC Refs
• Single or Dual 8-Bit 8:1 ADC
❐ Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
❐ Full Duplex UART, SPI™ Master or Slave
• Connectable to All GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Flexible On-Chip Memory
❐ 4K Flash Program Storage 50,000 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Complete Development Tools
❐ Free Development Software (PSoC Designer
™)
❐ Full Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 Bytes Trace Memory
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
■ Programmable Pin Configurations
❐ 25 mA Drive on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐ Up to Eight Analog Inputs on GPIO
❐ Configurable Interrupt on all GPIO
■ Additional System Resources
❐ I
2C™ Master, Slave and MultiMaster to 400 kHz
❐ Watchdog and Sleep Timers
❐ User Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
DIGITAL SYSTEM
SRAM
SystemBus
Interrupt
Controller
Sleep and
Watchdog
Clock Sources
(Includes IMO and ILO)
Global Digital Interconnect
Global Analog Interconnect
PSoC
CORE
CPU Core
(M8C)
SROM
Flash
I2C
Internal
Voltage
Ref.
Digital
Clocks
POR and LVD
System Resets
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref.
Port 1
Port 0
Digital
PSoC Block
Array
Analog
PSoC Block
Array
Sw itch
Mode
Pump
Logic Block Diagram
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