CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Document Number: 38-12025 Rev. *M
Page 2 of 43
PSoC® Functional Overview
The PSoC® family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
one low cost single-chip programmable component. A PSoC
device includes configurable blocks of analog and digital logic,
and programmable interconnect. This architecture enables the
user to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.
The PSoC architecture, shown in Figure 1, consists of four main
areas: the Core, the System Resources, the Digital System, and
the Analog System. Configurable global bus resources allow
combining all the device resources into a complete custom
system. Each CY8C21x34 PSoC device includes four digital
blocks and four analog blocks. Depending on the PSoC
package, up to 28 general purpose IO (GPIO) are also included.
The GPIO provide access to the global digital and analog inter-
connects.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard
architecture microprocessor.
System Resources provide the following additional capabilities:
■ Digital clocks to increase the flexibility of the PSoC
mixed-signal arrays.
■ I2C functionality to implement an I2C master and slave.
■ An internal voltage reference, MultiMaster, that provides an
absolute value of 1.3V to a number of PSoC subsystems.
■ A switch mode pump (SMP) that generates normal operating
voltages off a single battery cell.
■ Various system resets supported by the M8C.
The Digital System consists of an array of digital PSoC blocks
that may be configured into any number of digital peripherals.
The digital blocks are connected to the GPIO through a series of
global buses that can route any signal to any pin, freeing designs
from the constraints of a fixed peripheral controller.
The Analog System consists of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to 8
bits in precision.
The Digital System
The Digital System consists of 4 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or combined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user module references. Digital peripheral configurations include
the following.
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity
■ SPI master and slave
■ I2C slave and multi-master
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 4.
Figure 1. Digital System Block Diagram
DIGITAL SYSTEM
To System Bus
DigitalClocks
FromCore
Digital PSoC Block Array
ToAnalog
System
8
8
8
8
Row 0
DBB00
DBB01
DCB02
DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 3
Port 2
Port 1
Port 0
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