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MC8641VU1333J Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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MC8641VU1333J Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 140 page  MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 11 Electrical Characteristics 2.2 Power Up/Down Sequence The MPC8641 requires its power rails to be applied in a specific sequence in order to ensure proper device operation. NOTE The recommended maximum ramp up time for power supplies is 20 milliseconds. The chronological order of power up is: 1. All power rails other than DDR I/O (Dn_GVDD, and Dn_MVREF). NOTE There is no required order sequence between the individual rails for this item (# 1). However, VDD_PLAT, AVDD_PLAT rails must reach 90% of their recommended value before the rail for Dn_GVDD, and Dn_MVREF (in next step) reaches 10% of their recommended value. AVDD type supplies must be delayed with respect to their source supplies by the RC time constant of the PLL filter circuit described in Section 20.2.1, “PLL Power Supply Filtering”. 2. Dn_GVDD, Dn_MVREF NOTE It is possible to leave the related power supply (Dn_GVDD, Dn_MVREF) turned off at reset for a DDR port that will not be used. Note that these power supplies can only be powered up again at reset for functionality to occur on the DDR port. 3. SYSCLK The recommended order of power down is as follows: 1. Dn_GVDD, Dn_MVREF 2. All power rails other than DDR I/O (Dn_GVDD, Dn_MVREF). NOTE SYSCLK may be powered down simultaneous to either of item # 1 or # 2 in the power down sequence. Beyond this, the power supplies may power down simultaneously if the preservation of DDRn memory is not a concern. See Figure 3 for more details on the Power and Reset Sequencing details |
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