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MPC8313ECZQGDF Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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MPC8313ECZQGDF Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 100 page  MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1 10 Freescale Semiconductor Power Characteristics and VDDC) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies (I/O voltage and core voltage) are stable, wait for a minimum of 32 clock cycles before negating PORESET. Note that there is no specific power down sequence requirement for the MPC8313E. I/O voltage supplies (GVDD, LVDD, and OVDD) do not have any ordering requirements with respect to one another. Figure 3. Power-Up Sequencing Example 3 Power Characteristics The estimated typical power dissipation, not including I/O supply power, for this family of MPC8313E devices is shown in Table 4. Table 5 shows the estimated typical I/O power dissipation. Table 4. MPC8313E Power Dissipation1 1 The values do not include I/O supply power or AV DD, but do include core, USB PLL, and a portion of SerDes digital power (not including XCOREVDD, XPADVDD, or SDAVDD, which all have dedicated power supplies for the SerDes PHY). Core Frequency (MHz) CSB Frequency (MHz) Typical2 2 Typical power is based on a voltage of V DD = 1.05 V and an artificial smoker test running at room temperature. Maximum for Rev. 1.0 Silicon3 3 Maximum power is based on a voltage of V DD = 1.05 V, a junction temperature of TJ = 105°C, and an artificial smoker test. Maximum for Rev. 2.x or Later Silicon3 Unit 333 167 820 1020 1200 mW 400 133 820 1020 1200 mW t 90% V Core Voltage (VDD, VDDC) I/O Voltage (GVDD, GVDD, and OVDD) 0 0.7 V PORESET tSYS_CLK_IN/tPCI_SYNC_IN >= 32 clocks |
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