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MPC8313ZQAFDB Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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MPC8313ZQAFDB Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 100 page  MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1 Freescale Semiconductor 7 Electrical Characteristics 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 1 provides the absolute maximum ratings. 2.1.2 Power Supply Voltage Specification Table 2 provides the recommended operating conditions for the MPC8313E. Note that the values in Table 2 are the recommended and tested operating conditions. If a particular block is given a voltage falling within the range in the Recommended Value column, the MPC8313E is capable of delivering the Table 1. Absolute Maximum Ratings1 Characteristic Symbol Max Value Unit Notes Core supply voltage VDD –0.3 to 1.26 V — PLL supply voltage AVDD –0.3 to 1.26 V — Core power supply for SerDes transceivers XCOREVDD –0.3 to 1.26 V — Pad power supply for SerDes transceivers XPADVDD –0.3 to 1.26 V — DDR and DDR2 DRAM I/O voltage GVDD –0.3 to 2.75 –0.3 to 1.98 V— PCI, local bus, DUART, system control and power management, I2C, and JTAG I/O voltage NVDD/LVDD –0.3 to 3.6 V — eTSEC, USB LVDDA/LVDDB –0.3 to 3.6 V — Input voltage DDR DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2, 5 DDR DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2, 5 Enhanced three-speed Ethernet signals LVIN –0.3 to (LVDDA + 0.3) or –0.3 to (LVDDB + 0.3) V4, 5 Local bus, DUART, SYS_CLK_IN, system control, and power management, I2C, and JTAG signals OVIN –0.3 to (NVDD + 0.3) V 3, 5 PCI OVIN –0.3 to (NVDD + 0.3) V 6 Storage temperature range TSTG –55 to 150 °C— Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: OVIN must not exceed NVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: LVIN must not exceed LVDDA/LVDDB by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. |
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