MC8640HX1250N datasheet(3/8 Pages) FREESCALE

Part #	MC8640HX1250N

Description	Integrated Host Processor Hardware Specifications Addendum for the MC8640xTxxyyyyaC Series

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications Addendum for the MC8640xTxxyyyyaC

Series, Rev. 0

Freescale Semiconductor

3

General Parameters

11.2

JTAG AC Electrical Specifications

Table 43 provides the JTAG AC electrical specifications for the MPC8640 part numbers described herein.

Table 43. JTAG AC Timing Specifications (Independent of SYSCLK) 1

At recommended operating conditions (see Table 3).

Parameter

Symbol 2

Min

Max

Unit

Notes

Input setup times:

Boundary-scan data

TMS, TDI

tJTDVKH

tJTIVKH

15

0

—

ns

4

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal

in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-

Ω load

(see Figure 32). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state

(V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG

timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K)

going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters

representing the clock of a particular functional. For rise and fall times, the latter convention is used with the

appropriate letter: R (rise) or F (fall).

4. Non-JTAG signal input timing with respect to tTCLK.

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