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CY7B991V
3.3V RoboClock®
Document Number: 38-07141 Rev. *D
Page 7 of 13
Figure 9 shows the CY7B991V connected in series to construct a zero skew clock distribution tree between boards. Delays of the
downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay)
necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumulate
low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers in a
series.
Figure 8. Multi-Function Clock Driver
Figure 9. Board-to-Board Clock Distribution
20 MHz
DISTRIBUTION
CLOCK
80 MHz
INVERTED
Z0
20 MHz
80 MHz
ZERO SKEW
80 MHz
SKEWED –3.125 ns (–4tU)
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
LOAD
LOAD
LOAD
LOAD
Z0
Z0
Z0
SYSTEM
CLOCK
Z0
L1
L2
L3
L4
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
TEST
REF
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
FS
FB
LOAD
LOAD
LOAD
LOAD
LOAD
TEST
Z0
Z0
Z0
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