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PRELIMINARY
CY2DP818-2
Document #: 38-07588 Rev. *A
Page 7 of 9
Figure 5. Test Circuit and Voltage Definitions for the Differential Output Signal[2,3,4,5]
Figure 6. LVTTL/LVCMOS[6]
Figure 7. LVDS/LVPECL[6]
0.0V
100%
80%
20%
0%
tR
tF
1.4V
1.0V
VI(A)
VI(B)
TPA
TPC
TPB
50
50
GND
150
150
Standard Termination
Pulse
Generator
A
B
10pF
VDD-2V
1
InConfig
LVCMOS / LVTTL
LVTTL/LVCMOS
INPUT A
INPUT B
GND
In C o n fig
L VPE CL &
LV D S
L V DS /L V P E CL
0
Ordering Information
Part Number
Package Type
Product Flow
CY2DP818ZI-2
38-Pin TSSOP
Industrial, –40
° to 85°C
CY2DP818ZI-2T
38-Pin TSSOP–Tape and Reel
Industrial, –40
° to 85°C
CY2DP818ZC-2
38-Pin TSSOP
Commercial, 0
°C to 70°C
CY2DP818ZC-2T
38-Pin TSSOP–Tape and Reel
Commercial, 0
°C to 70°C
Pb Free Devices
CY2DP818ZXI-2
38-Pin TSSOP
Industrial, –40
° to 85°C
CY2DP818ZXI-2T
38-Pin TSSOP–Tape and Reel
Industrial, –40
° to 85°C
CY2DP818ZXC-2
38-Pin TSSOP
Commercial, 0
°C to 70°C
CY2DP818ZXC-2T
38-Pin TSSOP–Tape and Reel
Commercial, 0
°C to 70°C
Note
6. LVPECL or LVDS differential input value.
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