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MPC5533MZQ40 Datasheet(PDF) 9 Page - Freescale Semiconductor, Inc |
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MPC5533MZQ40 Datasheet(HTML) 9 Page - Freescale Semiconductor, Inc |
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9 / 50 page  Electrical Characteristics MPC5533 Microcontroller Data Sheet, Rev. 0.0 Freescale Semiconductor 9 3.5 ESD (Electromagnetic Static Discharge) Characteristics 3.6 Voltage Regulator Controller (VRC) and Power-On Reset (POR) Electrical Specifications The following table lists the VRC and POR electrical specifications: Table 5. ESD Ratings 1, 2 1 All ESD testing conforms to CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 Device failure is defined as: ‘If after exposure to ESD pulses, the device does not meet the device specification requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature. Characteristic Symbol Value Unit ESD for human body model (HBM) 2000 V HBM circuit description R1 1500 Ω C100 pF ESD for field induced charge model (FDCM) 500 (all pins) V 750 (corner pins) Number of pulses per pin: Positive pulses (HBM) Negative pulses (HBM) — — 1 1 — — Interval of pulses — 1 second Table 6. VRC/POR Electrical Specifications Spec Characteristic Symbol Min. Max. Units 11.5 V (VDD) POR 1 Negated (ramp up) Asserted (ramp down) VPOR15 1.1 1.1 1.35 1.35 V 23.3 V (VDDSYN) POR 1 Asserted (ramp up) Negated (ramp up) Asserted (ramp down) Negated (ramp down) VPOR33 0.0 2.0 2.0 0.0 0.30 2.85 2.85 0.30 V 3 RESET pin supply (VDDEH6) POR 1, 2 Negated (ramp up) Asserted (ramp down) VPOR5 2.0 2.0 2.85 2.85 V 4 VRC33 voltage Before VRC allows the pass transistor to start turning on VTRANS_START 1.0 2.0 V 5 When VRC allows the pass transistor to completely turn on 3, 4 VTRANS_ON 2.0 2.85 V 6 When the voltage is greater than the voltage at which the VRC keeps the 1.5 V supply in regulation 5, 6 VVRC33REG 3.0 — V Current can be sourced – 40o C11.0 — mA 7 by VRCCTL at Tj: 25o CIVRCCTL 7 9.0 — mA 150o C 7.5 — mA 8 Voltage differential during power up such that: VDD33 can lag VDDSYN or VDDEH6, before VDDSYN and VDDEH6 reach the VPOR33 and VPOR5 minimums respectively. VDD33_LAG —1.0 V |
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