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MMA621010AEG Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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MMA621010AEG Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
3 / 16 page MMA6222AEG Sensors Freescale Semiconductor 3 1.2 BLOCK DIAGRAM A block diagram illustrating the major components of the design is shown in Figure 1-2. Figure 1-2 MMA62XXAEG Block Diagram Figure 1-3 MMA62XXAEG DSP Block Diagram NOTE: Models of signal chain are available upon request VCC VSS ST STATUS SCLK RESET SELF-TEST CREG CREF VPP XOUT INTERFACE TEMP. SENSOR SD CONVERTER VOLTAGE REGULATOR g-CELL (Y) g-CELL (X) CONTROL LOGIC UNIT DATA ARRAY PROGRAMMABLE SD CONVERTER CLOCK INTERNAL MONITOR CREGA CAP/HOLD DAC YOUT Y IN X IN DIGITAL Y OUT X OUT DSP TEMP (SEE FIGURE 1-2) OUT CONTROL IN STATUS OUT DAC CREF CREGA VSSA CLOCK PRIMARY OSCILLATOR REFERENCE OSCILLATOR SINC FILTER SINC FILTER OFFSET, LOW-PASS FILTER TO X DAC GAIN, LINEARITY ADJUST OUTPUT SCALING DSP CONTROL TO Y DAC TEMP CONTROL IN OFFSET MONITOR Y IN X IN OUT |
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