MMA6222AEG

Sensors

Freescale Semiconductor

3

1.2

BLOCK DIAGRAM

A block diagram illustrating the major components of the design is shown in Figure 1-2.

Figure 1-2 MMA62XXAEG Block Diagram

Figure 1-3 MMA62XXAEG DSP Block Diagram

NOTE: Models of signal chain are available upon request

ST

STATUS

SCLK

RESET

SELF-TEST

INTERFACE

TEMP.

SENSOR

SD

CONVERTER

VOLTAGE

REGULATOR

g-CELL

(Y)

g-CELL

(X)

CONTROL

LOGIC

UNIT

DATA ARRAY

PROGRAMMABLE

SD

CONVERTER

CLOCK

INTERNAL

MONITOR

CAP/HOLD

DAC

Y IN

X IN

DIGITAL

Y OUT

X OUT

DSP

TEMP

(SEE FIGURE 1-2)

OUT

CONTROL

IN

STATUS

OUT

DAC

CLOCK

PRIMARY

OSCILLATOR

REFERENCE

OSCILLATOR

SINC

FILTER

SINC

FILTER

OFFSET,

LOW-PASS

FILTER

TO X DAC

GAIN,

LINEARITY

ADJUST

OUTPUT

SCALING

DSP

CONTROL

TO Y DAC

TEMP

CONTROL

IN

OFFSET

MONITOR

Y IN

X IN

OUT