SPI Programmable-Gain Amplifier

with Input Vos Trim and Output Op Amp

8

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CMRR, gain accuracy, and very low temperature drift

due to precise resistor matching. The output of this

This amplifier is followed by a programmable-gain

157V/V. The output of this amplifier is biased at

temperature drift.

The MAX9939 has an uncommitted op amp (amplifier

inverting input and output are externally accessible,

allowing it to be configured either as an active filter or

as a differential output.

A robust input ESD protection scheme allows input volt-

ages at INA+ and INA- to reach ±16V without damag-

ing the MAX9939, thus making the part extremely

attractive for use in front-ends that can be exposed to

high voltages during fault conditions. In addition, its

when powered from a 5V single supply) allowing the

MAX9939 to translate below ground signals to a 0V to

5V output signal. This feature simplifies interfacing

ground-referenced signals with unipolar-input ADCs.

SPI-Compatible Serial Interface

The MAX9939 has a write-only interface, consisting of

three inputs: the clock signal (SCLK), data input (DIN),

and chip-select input (

CS). The serial interface works

with the clock polarity (CPOL) and clock phase (CPHA)

both set to 0 (see Figure 1). Initiating a write to the

MAX9939 is accomplished by pulling

CS low. Data is

clocked in on the rising edge of each clock pulse, and

is written LSB first. Each write to the MAX9939 consists

of 8 bits (1 byte). Pull

CS high after the 8th bit has been

clocked in to latch the data and before sending the

next byte of instruction. Note that the internal register is

not updated if

CS is pulled high before the falling edge

of the 8th clock pulse.

Register Description

The MAX9939 consists of three registers: a shift register

and two internal registers. The shift register accepts

data and transfers it to either of the two internal regis-

ters. The two internal registers store data that is used to

determine the gain, input offset voltage, and operating

modes of the amplifier. The two internal registers are the

the 8-bit write to these registers is shown in Tables 1

and 2. Data is sent to the shift register LSB first.

SEL: The SEL bit selects which internal register is writ-

trim register. Set SEL to 1 to write D4:D1 to the Gain

register (D5 is don’t care when SEL = 1).

CS

SCLK

DIN

D7

D6

D5

D5

D4

D3

D2

D1

D0

Figure 2. SPI Interface Timing Diagram (CPOL = CPHA = 0)

D7

MSB

D6

D5

D4

D3

D2

D1

D0

LSB

SHDN MEAS

V4

V3

V2

V1

V0

SEL = 0

D7

MSB

D6

D5

D4

D3

D2

D1

D0

LSB

SHDN MEAS

X

G3

G2

G1

G0

SEL = 1

X = Don’t care.

Table 2. Gain Register