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MAX1322 Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX1322 Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 27 page INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE 12288 8192 4096 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 16384 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE 12288 8192 4096 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 16384 ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY VOLTAGE (V) 5.12 5.00 4.87 35 40 45 50 30 4.75 5.25 fSAMPLE = 250ksps ALL 8 CHANNELS DRIVEN WITH FULL- SCALE SINE WAVES ANALOG SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE (°C) 60 35 10 -15 35 40 45 50 30 -40 85 fSAMPLE = 250ksps ALL 8 CHANNELS DRIVEN WITH FULL- SCALE SINE WAVES SHUTDOWN CURRENT vs. SUPPLY VOLTAGE SUPPLY VOLTAGE (V) 4.5 3.5 0.2 0.4 0.6 0.8 0 2.5 5.5 ANALOG SHUTDOWN CURRENT DIGITAL SHUTDOWN CURRENT SHUTDOWN CURRENT vs. TEMPERATURE TEMPERATURE (°C) 60 35 10 -15 0.2 0.4 0.6 0.8 0 -40 85 ANALOG SHUTDOWN CURRENT DIGITAL SHUTDOWN CURRENT 8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges 6 _______________________________________________________________________________________ TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3) (continued) Note 7: Shutdown current is measured with analog input floating. The large amplitude of the maximum shutdown current specifi- cation is due to automatic test equipment limitations. Note 8: Defined as the change in positive full scale caused by ±5% variation in the nominal supply voltage. Note 9: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop. Note 10: CS-to-WR and CS-to-RD pins are internally AND together. Setup and hold times do not apply. Note 11: Minimum clock frequency is limited only by the internal T/H droop rate. Limit the time between the falling edge of CONVST to the falling edge of EOLC to a maximum of 0.25ms. Note 12: To avoid T/H droop degrading the sampled analog input signals, the first clock pulse should occur within 10µs of the ris- ing edge of CONVST, and have a minimum clock frequency of 100kHz. Typical Operating Characteristics (AVDD = +5V, DVDD = +3V, AGND = DGND = 0V, VREF = VREFMS = +2.5V (external reference), see the Typical Operating Circuits sec- tion, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.) |
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Similar Description - MAX1322 |
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