DDR Clock Oscillator

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3

ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

LVDS

Output High Voltage

100

differential load (Note 1)

1.475

V

Output Low Voltage

100

differential load (Note 1)

0.925

V

Differential Output Voltage

100

differential load

250

425

mV

Output Common-Mode Voltage

Variation

100

differential load

150

mV

Change in Differential Magnitude

or Complementary Inputs

100

differential load

25

mV

Offset Output Voltage

100

differential load (Note 1)

1.125

1.275

V

Differential Output Impedance

80

140

OUTN or OUTP shorted to ground and

measure the current in the shorting path

40

Output Current

OUTN or OUTP shorted together

6.5

mA

Output Rise Time (Differential)

20% to 80%

175

ps

Output Fall Time (Differential)

80% to 20%

175

ps

Duty Cycle

48

52

%

Propagation Delay from OE Going

Low to Logical 1 at OUTP

200

ns

Propagation Delay from OE Going

High to Output Active

200

ns

LVPECL

Output High Voltage

Output connected to 50

at PECL_BIAS

1.085

0.88

V

Output Low Voltage

Output connected to 50

at PECL_BIAS

1.825

1.62

V

Differential Voltage

Output connected to 50

at PECL_BIAS

0.595

0.710

V

Rise Time

200

ps

Fall Time

200

ps

Duty Cycle

48

52

%

Propagation Delay from OE Going

Low to Output High Impedance

200

ns

Propagation Delay from OE Going

High to Output Active

200

ns

Note 1: All voltages referenced to ground.

Note 2: AC parameters are guaranteed by design and not production tested.

Note 3: Frequency stability is calculated as: