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____________________________________________________________________________________________ DS3102 Rev: 102808 17 of 141 7. Functional Description 7.1 Overview The DS3102 has eight input clocks pins and three frame-sync input pins. The device can output as many as nine different clock frequencies on 16 output clock pins. There are two separate DPLLs in the device: the high- performance T0 DPLL and the simpler the T4 DPLL. Both DPLLs can generate output clocks. See Figure 3-1. Four of the input clock pins are single-ended and can accept clock signals from 2kHz to 125MHz. The other four are differential inputs that can accept clock signals up to 156.25MHz. The differential inputs can be configured to accept differential LVDS or LVPECL signals or single-ended CMOS/TTL signals. Each input clock can be monitored continually for activity and/or frequency. Frequency can be compared to both a hard limit and a soft limit. Inputs outside the hard limit are declared invalid, while inputs inside the hard limit but outside the soft limit are merely flagged. Each input can be marked unavailable or given a priority number. Separate input priority numbers are maintained for the T0 DPLL and the T4 DPLL. Except in special modes, the highest priority valid input is automatically selected as the reference for each path. SRFAIL is set or cleared based on activity and/or frequency of the selected input. Both the T0 DPLL and the T4 DPLL can directly lock to many common telecom and datacom frequencies, including, but not limited to, 8kHz, DS1, E1, 10MHz, 19.44MHz, and 38.88MHz as well as Ethernet frequencies including 25MHz, 62.5MHz, 125MHz, and 156.25MHz. The DPLLs can also lock to multiples of the standard direct- lock frequencies including 8kHz. The T0 DPLL is the high-performance path with all the features needed for line timing synchronization. The T4 DPLL is a simpler auxiliary path typically used to provide derived DS1s, E1s, or other synchronization signals to an external BITS/SSU. The T4 APLL can be connected to either the T4 DPLL or the T0 DPLL to provide extra low- jitter output frequencies from the T0 DPLL. There is also a dedicated low-jitter APLL output that operates at 312.5MHz for 10G Ethernet applications. Using the optional PLL bypass, the T4 selected reference, after any frequency division, can be directly output on any of the OC1 to OC7 output clock pins. Both DPLLs have these features: • Automatic reference selection based on input activity, quality, and priority • Optional manual reference selection/forcing • Configurable quality thresholds for each input • Adjustable PLL characteristics, including bandwidth, pull-in range, and damping factor • Ability to lock to several common telecom and Ethernet frequencies plus multiples of any standard direct lock frequency. • Frequency conversion between input and output using digital frequency synthesis • Combined performance of a stable, consistent digital PLL and low-jitter analog output PLLs The T0 DPLL has these additional features not available in the T4 DPLL: • A full state machine for automatic transitions among free-run, locked, and holdover states • Nonrevertive reference switching mode • Phase build-out for reference switching (“hitless”) and for phase hits on the selected reference • Output vs. input phase offset control • 21 bandwidth selections from 0.5mHz to 400Hz (vs. three selections for the T4 DPLL) • Noise rejection circuitry for low-frequency references • Output phase alignment to input frame-sync signal • Several frequency averaging methods for acquiring the holdover frequency The T4 DPLL has these additional features not available in the T0 DPLL: • Three bandwidth selections limited to 18Hz to 70Hz • Optional mode to measure the phase difference between two input clocks |
