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____________________________________________________________________________________________ DS3102 Rev: 102808 84 of 141 Register Name: MCLK1 Register Description: Master Clock Frequency Adjustment Register 1 Register Address: 3Ch Bit # 7 6 5 4 3 2 1 0 Name MCLKFREQ[7:0] Default 1 0 0 1 1 0 0 1 Note: The MCLK1 and MCLK2 registers must be read consecutively and written consecutively. See Section 8.3. Bits 7 to 0: Master Clock Frequency Adjustment (MCLKFREQ[7:0]). The full 16-bit MCLKFREQ[15:0] field spans this register and MCLK2. MCLKFREQ is an unsigned integer that adjusts the frequency of the internal 204.8MHz master clock with respect to the frequency of the local oscillator clock on the REFCLK pin by up to +514ppm and -771ppm. The master clock adjustment has the effect of speeding up the master clock with a positive adjustment and slowing it down with a negative adjustment. For example, if the oscillator connected to REFCLK has an offset of +1ppm, the adjustment should be -1ppm to correct the offset. The formulas below translate adjustments to register values and vice versa. The default register value of 39,321 corresponds to 0ppm. See Section 7.3. MCLKFREQ[15:0] = adjustment_in_ppm / 0.0196229 + 39,321 adjustment_in_ppm = (MCLKFREQ[15:0] – 39,321) × 0.0196229 Register Name: MCLK2 Register Description: Master Clock Frequency Adjustment Register 2 Register Address: 3Dh Bit # 7 6 5 4 3 2 1 0 Name MLCKFREQ[15:8] Default 1 0 0 1 1 0 0 1 Bits 7 to 0: Master Clock Frequency Adjustment (MCLKFREQ[15:8]). See the MCLK1 register description. |
