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____________________________________________________________________________________________ DS3102 Rev: 102808 78 of 141 Register Name: MCR5 Register Description: Master Configuration Register 5 Register Address: 36h Bit # 7 6 5 4 3 2 1 0 Name RSV[4:1] IC2SF IC1SF IC6SF IC5SF Default 0 0 0 0 0 0 0 0 Bits 7 to 4: Reserved Bits 4 to 1 (RSV[4:1]). These bits are reserved for future use. They can be written to and read back, but they should only be set to 0. Bit 3: Input Clock 2 Signal Format (IC2SF). For backward compatibility this bit can be written to and read back, but it does not affect the IC2POS/NEG inputs pins. See Section 7.4.1. Bit 2: Input Clock 1 Signal Format (IC1SF). For backward compatibility this bit can be written to and read back, but it does not affect the IC1POS/NEG inputs pins. See Section 7.4.1. Bit 1: Input Clock 6 Signal Format (IC6SF). For backward compatibility this bit can be written to and read back, but it does not affect the IC6POS/NEG inputs pins. See Section 7.4.1. Bit 0: Input Clock 5 Signal Format (IC5SF). For backward compatibility this bit can be written to and read back, but it does not affect the IC5POS/NEG inputs pins. See Section 7.4.1. |
