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____________________________________________________________________________________________ DS3102 Rev: 102808 70 of 141 Register Name: IPR1 Register Description: Input Priority Register 1 Register Address: 18h Bit # 7 6 5 4 3 2 1 0 Name PRI2[3:0] PRI1[3:0] Default (T0) 0 0 0 1 0 0 0 0 Default (T4) 0 0 0 1 0 0 0 0 Bits 7 to 4: Priority for Input Clock 2 (PRI2[3:0]). Priority 0001 is highest; priority 1111 is lowest. When MCR11:T4T0 = 0, PRI2 configures IC2’s priority for the T0 DPLL. When T4T0 = 1, PRI2 configures IC2’s priority for the T4 path. See Section 7.6.1. 0000 = IC2 unavailable for selection. 0001–1111= IC2 relative priority Bits 3 to 0: Priority for Input Clock 1 (PRI1[3:0]). Priority 0001 is highest; priority 1111 is lowest. When MCR11:T4T0 = 0, PRI1 configures IC1’s priority for the T0 DPLL. When T4T0 = 1, PRI1 configures IC1’s priority for the T4 path. See Section 7.6.1. 0000 = IC1 unavailable for selection. 0001–1111= IC1 relative priority Register Name: IPR2 Register Description: Input Priority Register 2 Register Address: 19h Bit # 7 6 5 4 3 2 1 0 Name PRI4[3:0] PRI3[3:0] Default (T0) 0 0 1 1 0 0 1 0 Default (T4) 0 0 1 1 0 0 1 0 Bits 7 to 4: Priority for Input Clock 4 (PRI4[3:0]). Priority 0001 is highest; priority 1111 is lowest. When MCR11:T4T0 = 0, PRI4 configures IC4’s priority for the T0 DPLL. When T4T0 = 1, PRI4 configures IC4’s priority for the T4 path. See Section 7.6.1. 0000 = IC4 unavailable for selection 0001–1111= IC4 relative priority Bits 3 to 0: Priority for Input Clock 3 (PRI3[3:0]). Priority 0001 is highest; priority 1111 is lowest. When MCR11:T4T0 = 0, PRI3 configures IC3’s priority for the T0 DPLL. When T4T0 = 1, PRI3 configures IC3’s priority for the T4 path. See Section 7.6.1. 0000 = IC3 unavailable for selection 0001–1111= IC3 relative priority |
