ABRIDGED DATA SHEET

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108

Rev: 101708

11 of 13

PIN NAME

TYPE

PIN DESCRIPTION

H_WR_BE2_N / SPI_SEL_N

I

Host Write Enable Byte 2 or SPI Chip Select (Active Low)

H_WR_BE3_N / SPI_CI

I

Host Write Enable Byte 3 (Active Low) or SPI Clock Invert

H_READY_N

Oz

Host Ready Output (Active Low)

H_INT

O

Host Interrupt Output.

JTAG Interface

JTRST_N

Ipu

JTAG Test Reset

JTCLK

Ipd

JTAG Test Clock

JTMS

Ipu

JTAG Test Mode Select

JTDI

Ipu

JTAG Test Data Input

JTDO

Oz

JTAG Test Data Output

Reset and Factory Test Pins

RST_SYS_N

Ipu

System Reset (Active Low)

HIZ_N

I

High Impedance Enable (Active Low)

SCEN

Ipd

Used for factory tests.

STMD

Ipd

Used for factory tests.

MBIST_EN

I

Used for factory tests.

MBIST_DONE

O

Used for factory tests.

MBIST_FAIL

O

Used for factory tests

TEST_CLK

O

Used for factory tests.

TST_CLD

I

Used for factory tests. DS34S104 only.

Power and Ground

DVDDC

P

1.8V Core Voltage for TDM-over-Packet Digital logic (17 pins)

DVDDIO

P

3.3V for I/O Pins (16 pins)

DVSS

P

Ground for TDM-over-Packet logic and I/O Pins (31 pins)

ACVDD1, ACVDD2

P

1.8V for CLAD Analog Circuits

ACVSS1, ACVSS2

P

Ground for CLAD Analog Circuits

Note 1:

In pin names, the suffix “n” stands for port number: n=1 to 8 for DS34S108; n=1 to 4 for DS34S104; n=2 for DS34S102; n=1 for

DS34S101. All pin names ending in “_N” are active low.

Note 2:

All pins, except power and analog pins, are CMOS/TTL unless otherwise specified in the pin description.

PIN TYPES

I = input pin

IO = input/output pin

O = output pin

P = power-supply or ground pin