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TLK3132 Datasheet(PDF) 2 Page - Texas Instruments |
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TLK3132 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 103 page  Contents TLK3132 2-Channel Multi-Rate Transceiver SLLS956 – DECEMBER 2008 www.ti.com 1 Introduction ......................................................................................................................... 9 1.1 Features ....................................................................................................................... 9 1.2 PIN OUT ...................................................................................................................... 9 1.3 Description .................................................................................................................. 10 2 Detailed Description ........................................................................................................... 11 2.1 Clocking Modes ............................................................................................................. 11 2.2 Operating Frequency Range .............................................................................................. 12 2.3 CPRI Latency Support ..................................................................................................... 12 2.4 Power-Down Mode ......................................................................................................... 12 2.5 Application Examples ...................................................................................................... 12 2.6 Device Operation Modes .................................................................................................. 17 2.7 Parallel Interface Modes - Detailed Description ........................................................................ 18 2.7.1 RGMII Mode (Reduced Gigabit Media Independent Interface) ............................................ 18 2.7.2 RTBI Mode (Reduced Ten Bit Interface) ..................................................................... 19 2.7.3 TBI Mode (Ten Bit Interface) ................................................................................... 20 2.7.4 GMII Mode (Gigabit Media Independent Interface) ......................................................... 21 2.7.5 EBI Mode (Eight Bit Interface) ................................................................................. 22 2.7.6 REBI Mode (Reduced Eight Bit Interface) ................................................................... 23 2.7.7 NBI Mode (Nine Bit Interface Mode) .......................................................................... 24 2.7.8 RNBI Mode (Reduced Nine Bit Interface) .................................................................... 25 2.7.9 TBID Mode (Ten Bit Interface DDR) .......................................................................... 26 2.7.10 NBID Mode (Nine Bit Interface DDR) ......................................................................... 27 2.7.11 Parallel Interface Clocking Modes ............................................................................. 28 2.7.12 Parallel to Serial ................................................................................................. 29 2.7.13 Serial to Parallel ................................................................................................. 29 2.7.14 High Speed CML Output ....................................................................................... 29 2.7.15 High Speed Receiver ........................................................................................... 31 2.7.16 Loopback ......................................................................................................... 31 2.7.17 Link Test Functions ............................................................................................. 31 2.7.18 MDIO Management Interface .................................................................................. 31 2.7.19 MDIO Protocol Timing .......................................................................................... 31 2.7.20 Clause 22 Indirect Addressing ................................................................................. 32 2.8 PROGRAMMERS REFERENCE ......................................................................................... 34 2.9 Top Level Programmers Reference ..................................................................................... 39 3 Device Reset Requirements/Procedure ................................................................................ 55 3.1 Gigabit Ethernet Mode (RGMII) .......................................................................................... 55 3.2 JITTER TEST PATTERN GENERATION AND VERIFICATION PROCEDURES ................................. 58 3.3 PRBS Test Generation and Verification Procedures ................................................................. 60 3.4 Signal Pin Description ..................................................................................................... 63 4 Electrical Specifications ...................................................................................................... 69 4.1 ABSOLUTE MAXIMUM RATINGS ....................................................................................... 69 4.2 RECOMMENDED OPERATING CONDITIONS ........................................................................ 69 4.3 REFERENCE CLOCK TIMING REQUIREMENTS (REFCLKP/N) .................................................. 70 4.4 REFERENCE CLOCK ELECTRICAL CHARACTERISTICS (REFCLKP/N) ........................................ 70 4.5 SINGLE ENDED REFERENCE CLOCK ELECTRICAL CHARACTERISTICS (REFCLK) ....................... 70 4.6 JITTER CLEANER TIMING PARAMETERS ........................................................................... 71 4.7 LVCMOS ELECTRICAL CHARACTERISTICS ......................................................................... 71 4.8 MDIO ELECTRICAL CHARACTERISTICS ............................................................................. 71 4.9 HSTL SIGNALS (VDDQ = 1.5/1.8 V) ................................................................................... 72 4.10 SERIAL TRANSMITTER/RECEIVER CHARACTERISTICS ......................................................... 73 Contents 2 Submit Documentation Feedback |
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