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AD9522-5 Datasheet(PDF) 2 Page - Analog Devices |
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AD9522-5 Datasheet(HTML) 2 Page - Analog Devices |
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2 / 76 page  AD9522-5 Rev. 0 | Page 2 of 76 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 7 Clock Outputs ............................................................................... 7 Timing Characteristics ................................................................ 8 Timing Diagrams ..................................................................... 8 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ........................................................................ 9 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ......................................................................... 10 Clock Output Additive Time Jitter (VCO Divider Not Used) ....................................................................................................... 10 Clock Output Additive Time Jitter (VCO Divider Used) ..... 11 Serial Control Port—SPI Mode ................................................ 11 Serial Control Port—I2C Mode ................................................ 12 PD, SYNC, and RESET Pins ..................................................... 13 Serial Port Setup Pins: SP1, SP0 ............................................... 13 LD, STATUS, and REFMON Pins............................................ 13 Power Dissipation....................................................................... 14 Absolute Maximum Ratings.......................................................... 15 Thermal Resistance .................................................................... 15 ESD Caution................................................................................ 15 Pin Configuration and Function Descriptions........................... 16 Typical Performance Characteristics ........................................... 19 Terminology .................................................................................... 23 Detailed Block Diagram ................................................................ 24 Theory of Operation ...................................................................... 25 Operational Configurations...................................................... 25 Mode 1: Clock Distribution or External VCO < 1600 MHz ................................................................................................... 25 Mode 2: High Frequency Clock Distribution—CLK or External VCO > 1600 MHz .................................................. 27 Phase-Locked Loop (PLL) .................................................... 29 Configuration of the PLL ...................................................... 29 Phase Frequency Detector (PFD) ........................................ 29 Charge Pump (CP)................................................................. 29 PLL External Loop Filter....................................................... 30 PLL Reference Inputs............................................................. 30 Reference Switchover............................................................. 30 Reference Divider R............................................................... 31 VCO/VCXO Feedback Divider N: P, A, B .......................... 31 Digital Lock Detect (DLD) ................................................... 32 Analog Lock Detect (ALD)................................................... 32 Current Source Digital Lock Detect (CSDLD) .................. 32 External VCXO/VCO Clock Input (CLK/CLK) ................ 33 Holdover.................................................................................. 33 External/Manual Holdover Mode........................................ 33 Automatic/Internal Holdover Mode.................................... 34 Frequency Status Monitors ................................................... 35 Zero Delay Operation................................................................ 37 Clock Distribution ..................................................................... 38 Operation Modes ................................................................... 38 Clock Frequency Division..................................................... 38 VCO Divider........................................................................... 39 Channel Dividers ................................................................... 39 Synchronizing the Outputs—SYNC Function ................... 41 LVDS Output Drivers ............................................................ 42 CMOS Output Drivers .......................................................... 43 Reset Modes ................................................................................ 43 Power-On Reset...................................................................... 43 Hardware Reset via the RESET Pin ..................................... 43 Soft Reset via the Serial Port................................................. 43 Soft Reset to Settings in EEPROM When EEPROM Pin = 0 via the Serial Port ................................................................... 43 Power-Down Modes .................................................................. 43 Chip Power-Down via PD .................................................... 43 PLL Power-Down................................................................... 44 Distribution Power-Down .................................................... 44 Individual Clock Output Power-Down............................... 44 Individual Clock Channel Power-Down............................. 44 Serial Control Port ......................................................................... 45 SPI/I2C Port Selection................................................................ 45 I2C Serial Port Operation .......................................................... 45 I2C Bus Characteristics .......................................................... 45 Data Transfer Process ............................................................ 46 |
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