AD9520-0BCPZ-REEL7 datasheet(2/84 Pages) AD

Part #	AD9520-0BCPZ-REEL7

Description	12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

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AD9520-0

Rev. 0 | Page 2 of 84

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Power Supply Requirements ....................................................... 4

PLL Characteristics ...................................................................... 4

Clock Inputs .................................................................................. 7

Clock Outputs ............................................................................... 7

Timing Characteristics ................................................................ 8

Timing Diagrams ..................................................................... 9

Clock Output Additive Phase Noise (Distribution Only;

VCO Divider Not Used) ............................................................ 10

Clock Output Absolute Phase Noise (Internal VCO Used).. 11

Clock Output Absolute Time Jitter (Clock Generation

Using Internal VCO).................................................................. 11

Clock Output Absolute Time Jitter (Clock Cleanup

Using Internal VCO).................................................................. 11

Clock Output Absolute Time Jitter (Clock Generation

Using External VCXO) .............................................................. 12

Clock Output Additive Time Jitter (VCO Divider

Not Used)..................................................................................... 12

Clock Output Additive Time Jitter (VCO Divider Used) ..... 13

Serial Control Port—SPI Mode ................................................ 13

Serial Control Port—I2C Mode ................................................ 14

PD, SYNC, and RESET Pins ..................................................... 15

Serial Port Setup Pins: SP1, SP0 ............................................... 15

LD, STATUS, and REFMON Pins............................................ 15

Power Dissipation....................................................................... 16

Absolute Maximum Ratings.......................................................... 17

Thermal Resistance .................................................................... 17

ESD Caution................................................................................ 17

Pin Configuration and Function Descriptions........................... 18

Typical Performance Characteristics ........................................... 21

Terminology .................................................................................... 26

Detailed Block Diagram ................................................................ 27

Theory of Operation ...................................................................... 28

Operational Configurations...................................................... 28

Mode 0: Internal VCO and Clock Distribution ................. 28

Mode 1: Clock Distribution or External VCO

<1600 MHz ............................................................................. 30

Mode 2: High Frequency Clock Distribution—

CLK or External VCO > 1600 MHz .................................... 32

Phase-Locked Loop (PLL) .................................................... 34

Configuration of the PLL ...................................................... 34

Phase Frequency Detector (PFD) ........................................ 34

Charge Pump (CP)................................................................. 35

On-Chip VCO ........................................................................ 35

PLL External Loop Filter....................................................... 35

PLL Reference Inputs............................................................. 35

Reference Switchover............................................................. 36

Reference Divider R............................................................... 36

VCO/VCXO Feedback Divider N: P, A, B, R ..................... 36

Digital Lock Detect (DLD) ................................................... 38

Analog Lock Detect (ALD)................................................... 38

Current Source Digital Lock Detect (CSDLD) .................. 38

External VCXO/VCO Clock Input (CLK/CLK) ................ 39

Holdover.................................................................................. 39

External/Manual Holdover Mode........................................ 39

Automatic/Internal Holdover Mode.................................... 39

Frequency Status Monitors ................................................... 41

VCO Calibration .................................................................... 42

Zero Delay Operation................................................................ 43

Internal Zero Delay Mode..................................................... 43

External Zero Delay Mode.................................................... 43

Clock Distribution ..................................................................... 44

Operation Modes ................................................................... 44

CLK or VCO Direct-to-LVPECL Outputs.......................... 44

Clock Frequency Division..................................................... 45

VCO Divider........................................................................... 45

Channel Dividers ................................................................... 45

Synchronizing the Outputs—SYNC Function ................... 47

LVPECL Output Drivers ....................................................... 49

CMOS Output Drivers .......................................................... 49

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