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AD9239-250KITZ Datasheet(PDF) 9 Page - Analog Devices |
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AD9239-250KITZ Datasheet(HTML) 9 Page - Analog Devices |
9 / 40 page AD9239 Rev. 0 | Page 9 of 40 PIN CONFIGURATION AND FUNCTION DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC TEMPOUT RBIAS AVDD NC NC AVDD VCM D AVDD VIN – D VIN + D AVDD AVDD AVDD AVDD CLK– 17 CLK+ 18 AVDD 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 NC PGM0 PGM1 PGM2 PGM3 NC AVDD VCM A AVDD VIN – A VIN + A AVDD AVDD AVDD CSB SCLK SDI/SDIO SDO PIN 1 INDICATOR AD9239 TOP VIEW (Not to Scale) PIN 0 = EPAD = AGND NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE CUSTOMER BOARD INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING THE THERMAL CAPABILITY OF THE PACKAGE. Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 0 AGND Analog Ground (Exposed Paddle). 23, 34 DRGND Digital Output Driver Ground. 4, 7, 9, 12, 13, 14, 15, 18, 20, 21, 41, 42, 43, 46, 48, 55, 57, 60, 61, 62, 64, 65, 66, 69, 71 AVDD 1.8 V Analog Supply. 24, 33 DRVDD 1.8 V Digital Output Driver Supply. 2 TEMPOUT Output Voltage to Monitor Temperature. 3 RBIAS External Resistor to Set the Internal ADC Core Bias Current. 8 VCM D Common-Mode Output Voltage Reference (0.5 × AVDD). 10 VIN − D ADC D Analog Complement. 11 VIN + D ADC D Analog True. 16 CLK− Input Clock Complement. 17 CLK+ Input Clock True. 22 RESET Digital Output Timing Reset. 25 DOUT + D ADC D True Digital Output. 26 DOUT − D ADC D Complement Digital Output. 27 DOUT + C ADC C True Digital Output. 28 DOUT − C ADC C Complement Digital Output. 29 DOUT + B ADC B True Digital Output. 30 DOUT − B ADC B Complement Digital Output. 31 DOUT + A ADC A True Digital Output. 32 DOUT − A ADC A Complement Digital Output. 35 PDWN Power-Down. |
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