Freescale Semiconductor

10

Table 6 lists the clock operation.

1.1.8

Reset, Stop, Mode Select, and Interrupt Timing

Table 7 lists the reset, stop, mode select, and interrupt timing.

Table 6. Clock Operation

No.

Characteristics

Symbol

Min

Max

Units

6

(40% to 60% duty cycle)

• Crystal oscillator

• Square wave input

Eth

16.67

2.5

100

inf

ns

7

(40% to 60% duty cycle)

• Crystal oscillator

• Square wave input

Etl

16.67

2.5

100

inf

ns

8

EXTAL cycle time

• With PLL disabled

• With PLL enabled

Etc

5

33.3

inf

500

ns

9

Instruction cycle time

• With PLL disabled

• With PLL enabled

Tc

5

inf

5120

ns

Note:

1. Measured at 50% of the input transition.

2. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time

required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock

frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low

time requirements are met.

Table 7. Reset, Stop, Mode Select, and Interrupt Timing

No.

Characteristics

Expression

Min

Max

Unit

10

——

11

ns

11

• Power on, external clock generator, PLL disabled

• Power on, external clock generator, PLL enabled

2

10

—

ns

2

10

—

ns

13

Syn reset deassert delay time

• Minimum

2

10

—

ns

• Maximum (PLL enabled)

200

—

us

14

Mode select setup time

—

10

—

ns

15

Mode select hold time

—

12

—

ns

16

Minimum edge-triggered interrupt request assertion width

—

7

—

ns

17

Minimum edge-triggered interrupt request deassertion width

—

4

—

ns

18

Delay from interrupt trigger to interrupt code execution

10

54

—

ns