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LTC2308CUFXTRPBF Datasheet(PDF) 11 Page - Linear Technology |
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LTC2308CUFXTRPBF Datasheet(HTML) 11 Page - Linear Technology |
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11 / 20 page  LTC2308 11 2308f APPLICATIONS INFORMATION Overview The LTC2308 is a low noise, 500ksps, 8-channel, 12-bit successive approximation register (SAR) A/D converter. The LTC2308 includes a precision internal reference, a configurable 8-channel analog input multiplexer (MUX) and an SPI-compatible serial port for easy data transfers. The ADC may be configured to accept single-ended or differential signals and can operate in either unipolar or bipolar mode. A sleep mode option is also provided to save power during inactive periods. Conversions are initiated by a rising edge on the CONVST input. Once a conversion cycle has begun, it cannot be restarted. Between conversions, a 6-bit input word (DIN) at the SDI input configures the MUX and programs vari- ous modes of operation. As the DIN bits are shifted in, data from the previous conversion is shifted out on SDO. After the 6 bits of the DIN word have been shifted in, the ADC begins acquiring the analog input in preparation for the next conversion as the rest of the data is shifted out. The acquire phase requires a minimum time of 240ns for the sample-and-hold capacitors to acquire the analog input signal. During the conversion, the internal 12-bit capacitive charge-redistribution DAC output is sequenced through a successive approximation algorithm by the SAR starting from the most significant bit (MSB) to the least significant bit (LSB). The sampled input is successively compared with binary weighted charges supplied by the capacitive DAC using a differential comparator. At the end of a conver- sion, the DAC output balances the analog input. The SAR contents (a 12-bit data word) that represent the sampled analog input are loaded into 12 output latches that allow the data to be shifted out. Programming the LTC2308 The various modes of operation of the LTC2308 are programmed by a 6-bit DIN word. The SDI data bits are loaded on the rising edge of SCK, with the S/D bit loaded on the first rising edge and the SLP bit on the sixth rising edge (see Figure 8 in the Timing and Control section). The input data word is defined as follows: S/D O/S S1 S0 UNI SLP S/D = SINGLE-ENDED/DIFFERENTIAL BIT O/S = ODD/SIGN BIT S1 = ADDRESS SELECT BIT 1 S0 = ADDRESS SELECT BIT 0 UNI = UNIPOLAR/BIPOLAR BIT SLP = SLEEP MODE BIT |
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