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TDA7522 Datasheet(PDF) 5 Page - STMicroelectronics |
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TDA7522 Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 23 page 5/23 TDA7522 33 TESTEN I Test enable signal (Active low) 34 SCK I IIC I/F clock signal 35 SDA I/O IIC I/F data 36 SCANEN I Scan enable (active high) or select DRAM outputs as TEST outputs when TESTEN is inactive 37 KASEL I/O DAC polarity selection pin or ST7 GPIO PA0 38 KTEST I/O User test mode selection or ST7 GPIO PA1 39 KSEARCH I/O Gain change during search or ST7 GPIO PA3 40 MSTOP I/O interrupt request/stand-by pin or ST7 GPIO PC5 41 SLEDL I/O SLED limit switch or ST7 GPIO PC6 42 K_VER_HOR I/O Indication of vertical or horizontal operation or ST7 GPIO PA4 43 WFCK O Write Frame clock for Subcode P-W output 44 EXCK I SBSO readout clock input 45 SBSO O Subcode P-W serial output 46 SCOR O Subcode sync output 47 DOUT O SPDIF Digital audio output 48 CS I/O ST7 GPIO PC4 49 SRQ I/O ST7 GPIO PC3 50 CORE_VDD_3 Vdd Digital Power supply 51 CORE_VSS_3 Gnd Digital Ground 52 DATAS I/O ST7 GPIO PC2 53 DATAM I/O ST7 GPIO PC1 54 CLK I/O ST7 GPIO PC0 55 DRS I/O Shock proof memory Read control 56 DWR I/O Shock proof memory Write control 57 CAS I/O Shock proof memory Column address select 58 RAS I/O Shock proof memory Row address select 59 DRA11 I/O DRAM Address 11 60 DRA10 I/O DRAM Address 10 61 DRA9 I/O DRAM Address 9 or Mirror signal output 62 DRA8 I/O DRAM Address 8 or TZC (Tracking Zero Cross) signal output 63 DRA7 I/O DRAM Address 7 or FOK (Focus OK) signal output 64 DRA6 I/O DRAM Address 6 or ST7 GPIO PB7 or PLLINF signal output Pin Number Name Function Description |
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