LV24230LP-A

No.A0891-9/17

(3). Register description (ON Contents of each Register)

Register 00h – CHIP_ID – Chip identify register (Read/Write)

7

6

5

4

3

2

1

0

ID [7 : 0]

bit 7-0 :

ID [7 : 0] : 8-bit chip ID.

LV24230LP-A : 12h

Note : To abort the command, write any value in this register.

Register 02h – RADIO_STAT – Radio station status (Read-Only)

7

6

5

4

3

2

1

0

RAD_IF

N/A

N/A

MO_ST

FS [2 : 0]

SF5DB

bit 7 :

RAD_IF : Radio interrupt flag.

0 = no interrupt

1 = interrupt

Note :

When status (field strength, stereo/mono) changes, this bit is set.

If Interrupt of IRQ pin is enabled, Interrupt pin is set by following IPOL register condition.

This bit is cleared by register read. In stand-by mode (PW_RAD = 0), this bit is 1

bit 6-5 :

NA [1 : 0] : NA 0 fixed

bit 4 :

MO_ST : Mono/stereo indicator

0 = Forced monaural

1 = Normal (Receiving in stereo mode)

bit 3-1

FS [2 : 0] : Fieldstrength :

0 = Low field strength

…

7 = High field strength

bit 0 :

SF5DB : Fieldstrength +5dB :

0 = FS5dB no UP

1 = FS5dB UP

For details, refer to Application note.

Register 0Bh – RFCAP – RF Cap bank (Read/Write)

7

6

5

4

3

2

1

0

RFCAP [7 : 0]

bit 7-0 :

RFCAP [7 : 0] : RF Oscillator CAP bank