LV5710V

PS No.A1117-6/6

Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the

performance, characteristics, and functions of the described products in the independent state, and are

not guarantees of the performance, characteristics, and functions of the described products as mounted

in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an

independent device, the customer should always evaluate and test devices mounted in the customer's

products or equipment.

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protective circuits and error prevention circuits for safe design, redundant design, and structural design.

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Startup sequence

EN Pin and VDD

The sequence operation is made at startup. However, startup is not made when the internal circuit has not been reset.

To reset the internal circuit, keep the EN pin to “L” till VDD becomes 4.5V or more.

Note that VDD and EN pin cannot be short-circuited for this purpose.

This catalog provides information as of March, 2008. Specifications and information herein are subject

to change without notice.

Frequency selection

S0

VDD

EN

Charge pump

output CPO

Regulator

output RO

* CP clock 1MHz

* CP clock 500kHz

* CP clock 250kHz

* CP clock 125kHz

* IC internal signal

Start at 1MHz

Steady operation

Start at 1MHz

SS end

10ms (max)

SS end

10ms (max)

Steady operation

Do not allow the signal to change

Frequency selection

Frequency selection

Do not allow the signal to change

Frequency selection

Do not allow the signal to change

Frequency selection

Frequency selection

Do not allow the signal to change

S1

Set EN = H after setting

VDD = 4.5V or more

Never allow VDD to decrease below

4.5V till EN = L is established

Stop with EN = L or for over-

current protection