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M38044F5KP Datasheet(PDF) 9 Page - Renesas Technology Corp

Part # M38044F5KP
Description  8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
Download  387 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M38044F5KP Datasheet(HTML) 9 Page - Renesas Technology Corp

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3804 Group (Spec.H)
List of figures
REJ09B0212-0100Z
Rev.1.00
Jan 14, 2005
List of figures
CHAPTER 1 HARDWARE
Fig. 1 3804 group (Spec. H) pin configuration ........................................................................ 1-3
Fig. 2 3804 group (Spec. H) pin configuration ........................................................................ 1-3
Fig. 3 Functional block diagram ................................................................................................. 1-4
Fig. 4 Part numbering .................................................................................................................. 1-6
Fig. 5 Memory expansion plan ................................................................................................... 1-7
Fig. 6 740 Family CPU register structure ................................................................................. 1-8
Fig. 7 Register push and pop at interrupt generation and subroutine call .......................... 1-9
Fig. 8 Structure of CPU mode register ................................................................................... 1-11
Fig. 9 Structure of MISRG ........................................................................................................ 1-12
Fig. 10 Memory map diagram ................................................................................................... 1-13
Fig. 11 Memory map of special function register (SFR) ...................................................... 1-14
Fig. 12 Port block diagram (1) ................................................................................................. 1-16
Fig. 13 Port block diagram (2) ................................................................................................. 1-17
Fig. 14 Port block diagram (3) ................................................................................................. 1-18
Fig. 15 Structure of port pull-up control register (1) ............................................................. 1-19
Fig. 16 Structure of port pull-up control register (2) ............................................................. 1-20
Fig. 17 Structure of port pull-up control register (3) ............................................................. 1-21
Fig. 18 Structure of port pull-up control register (4) ............................................................. 1-22
Fig. 19 Interrupt control ............................................................................................................. 1-25
Fig. 20 Structure of interrupt-related registers ....................................................................... 1-26
Fig. 21 Block diagram of timer X, timer Y, timer 1, and timer 2 ........................................ 1-29
Fig. 22 Structure of timer XY mode register .......................................................................... 1-30
Fig. 23 Structure of timer 12, X and timer Y, Z count source selection registers ........... 1-31
Fig. 24 Block diagram of timer Z ............................................................................................. 1-35
Fig. 25 Structure of timer Z mode register ............................................................................. 1-36
Fig. 26 Timing chart of timer/event counter mode ................................................................ 1-37
Fig. 27 Timing chart of pulse output mode ............................................................................ 1-37
Fig. 28 Timing chart of pulse period measurement mode (Measuring term between two rising edges) .. 1-38
Fig. 29 Timing chart of pulse width measurement mode (Measuring “L” term) ................ 1-38
Fig. 30 Timing chart of programmable waveform generating mode ................................... 1-39
Fig. 31 Timing chart of programmable one-shot generating mode (“H” one-shot pulse generating) ... 1-39
Fig. 32 Block diagram of clock synchronous serial I/O1 ...................................................... 1-40
Fig. 33 Operation of clock synchronous serial I/O1 .............................................................. 1-40
Fig. 34 Block diagram of UART serial I/O1 ............................................................................ 1-41
Fig. 35 Operation of UART serial I/O1 ................................................................................... 1-41
Fig. 36 Structure of serial I/O1 control registers ................................................................... 1-43
Fig. 37 Structure of serial I/O2 control register ..................................................................... 1-46
Fig. 38 Block diagram of serial I/O2 ....................................................................................... 1-46
Fig. 39 Timing of serial I/O2 ..................................................................................................... 1-47
Fig. 40 Block diagram of clock synchronous serial I/O3 ...................................................... 1-48
Fig. 41 Operation of clock synchronous serial I/O3 .............................................................. 1-48
Fig. 42 Block diagram of UART serial I/O3 ............................................................................ 1-49
Fig. 43 Operation of UART serial I/O3 ................................................................................... 1-49
Fig. 44 Structure of serial I/O3 control registers ................................................................... 1-51
Fig. 45 Timing of PWM period ................................................................................................. 1-54
Fig. 46 Block diagram of PWM function ................................................................................. 1-54


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