LC87F2708A

No.A1335-10/21

Allowable Operating Range at Ta = -40

°C to +85°C, VSS1 = 0V

Specification

Parameter

Symbol

Pin/Remarks

Conditions

VDD[V]

min

typ

max

unit

Operating

supply voltage

(Note 2-1)

VDD

VDD1

0.272

μs ≤ tCYC ≤ 100μs

2.7

5.5

Memory

sustaining

supply voltage

VHD

VDD1

RAM and register contents sustained

in HOLD mode

2.0

5.5

VIH(1)

• Port 1

• Port 3

Output disabled

2.7 to 5.5

0.3VDD

+0.7

VDD

High level

input voltage

VIH(2)

RES

2.7 to 5.5

0.75VDD

VDD

4.0 to 5.5

VSS

0.1VDD

+0.4

VIL(1)

• Port 1

• Port 3

Output disabled

2.7 to 4.0

VSS

0.2VDD

Low level

input voltage

VIL(2)

RES

2.7 to 5.5

VSS

0.25VDD

V

Instruction

cycle time

(Note 2-2)

tCYC

2.7 to 5.5

0.272

100

μs

FmHRC(1)

• High-speed RC oscillation

• 40MHz selected as option

• Ta=-20°C to +85°C

4.5 to 5.5

38

40

42

FmHRC(2)

4.5 to 5.5

37.6

40

42.4

FmHRC(3)

3.5 to 5.5

36.8

40

43.2

FmHRC(4)

• High-speed RC oscillation

• 40MHz selected as option

• Ta=-40°C to +85°C

2.7 to 5.5

32

40

43.2

FmHRC(5)

• High-speed RC oscillation

• 20MHz selected as option

• Ta=-20°C to +85°C

3.0 to 5.5

19

20

21

FmHRC(6)

• High-speed RC oscillation

• 20MHz selected as option

• Ta=-40°C to +85°C

2.7 to 5.5

18.7

20

21.3

FmRC

Medium-speed RC oscillation

2.7 to 5.5

0.5

1.0

2.0

MHz

Oscillation

frequency

range

FmSLRC

Low-speed RC oscillation

2.7 to 5.5

15

30

60

kHz

Oscillation

stabilization

time

tmsHRC

• When high-speed RC oscillation

state is switched from stopped to

enabled.

• See Fig. 2.

2.7 to 5.5

100

μs

Note 2-1: Use this product in a voltage range of 3.0 to 5.5V because the minimum release voltage (PORRL) of the

power-on reset (POR) circuit is 2.87V

±0.12V.

Note 2-2: Relationship between tCYC and oscillation frequency is as follows:

• When system clock source is set to medium-speed RC oscillation

3/FmRC at a division ratio of 1/1, 6/FmRC at a division ratio of 1/2, 12/FmRC a division ratio of 1/4, and so

forth

• When system clock source is set to high-speed RC oscillation (40MHz selected by optional configuration)

12/FmHRC at a division ratio of 1/1, 24/FmHRC at a division ratio of 1/2, 48/FmHRC a division ratio of 1/4,

and so forth

• When system clock source is set to high-speed RC oscillation (20MHz selected by optional configuration)

6/FmHRC at a division ratio of 1/1, 12/FmHRC at a division ratio of 1/2, 24/FmHRC a division ratio of 1/4,

and so forth