Electronic Components Datasheet Search |
|
UCD9240PFCR Datasheet(PDF) 4 Page - Texas Instruments |
|
|
UCD9240PFCR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 38 page UCD9240 SLUS766B – JULY 2008 – REVISED AUGUST 2008......................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT DIGITAL INPUTS/OUTPUTS Dgnd VOL Low-level output voltage IOH = 6 mA (2), V V33DIO = 3 V V +0.25 V33DIO VOH High-level output voltage IOH = -6 mA (3), V V33DIO = 3 V V -0.6V VIH High-level input voltage VV33DIO = 3V 2.1 V VIL Low-level input voltage VV33DIO = 3.5 V 1.1 V FAN CONTROL INPUTS/OUTPUTS TPWM_PERIOD FAN-PWM period 156 kHz DUTYPWM FAN-PWM duty cycle range 0% 100% DUTYRES Duty cycle resolution 1% For 1 Tach pulse per revolution. At 2, TachRANGE FAN-TACH range 30 300k RPM 3, or 4 pulse/rev, divide by that value TachRES FAN-TACH resolution For 1 Tach pulse per revolution 30 RPM tMIN FAN-TACH minimum pulse width Either positive or negative polarity 150 µs SYSTEM PERFORMANCE Vref commanded to be 1V, at 25 °C VRef Setpoint Reference Accuracy -10 10 mV AFEgain = 4, 1V input to EAP/N measured at output of the EADC(4) Setpoint Reference Accuracy over -40 °C to 125 °C -20 20 mV temeprature AFEgain = 4 compared to Differential offset between gain VDiffOffset -4 4 mV setetings AFEgain = 1, 2, or 8 tDelay Digital Compensator Delay(5) 208(6) ns FSW Switching Frequency 15.260 2000 kHz Duty Max and Min Duty Cycle Configured via PMBus 0% 100% VDDSlew Minimum VDD slew rate VDD slew rate between 2.3V and 2.9V 0.25 V/ms tretention Retention of configuration parameters TJ = 25 °C 100 Years Number of nonvolatile erase/write Write_Cycles TJ = 25 °C 20 K cycles cycles (2) The maximum total current, IOH max and IOL max, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. (3) The maximum total current current, IOH max and IOL max, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified. (4) With default device caliibration. PMBus calibration can be used to improve the regulation tolerance. (5) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay must be accounted for when calculating the system dynamic response. (6) The PMBus command: EADC_SAMPLE_TRIGGER defines the start of the 32ns ADC sample window. So the minimum EAD_SAMPLE_TRIGGER time is 208 + 32 = 240 ns. 4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCD9240 |
Similar Part No. - UCD9240PFCR |
|
Similar Description - UCD9240PFCR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |