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M38C37M8MXXXFP Datasheet(PDF) 10 Page - Renesas Technology Corp |
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M38C37M8MXXXFP Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 224 page 4 38C3 Group User’s Manual List of figures List of figures CHAPTER 1 HARDWARE Fig. 1 M38C34M6AXXXFP pin configuration .............................................................................. 1-2 Fig. 2 Functional block diagram ................................................................................................... 1-3 Fig. 3 Part numbering .................................................................................................................... 1-6 Fig. 4 Memory expansion plan ..................................................................................................... 1-7 Fig. 5 740 Family CPU register structure ................................................................................... 1-8 Fig. 6 Register push and pop at interrupt generation and subroutine call ........................... 1-9 Fig. 7 Structure of CPU mode register ..................................................................................... 1-11 Fig. 8 Memory map diagram ...................................................................................................... 1-12 Fig. 9 Memory map of special function register (SFR) .......................................................... 1-13 Fig. 10 Structure of PULL register A and PULL register B ................................................... 1-14 Fig. 11 Structure of port P8 output selection register ............................................................ 1-14 Fig. 12 Port block diagram (1) ................................................................................................... 1-16 Fig. 13 Port block diagram (2) ................................................................................................... 1-17 Fig. 14 Port block diagram (3) ................................................................................................... 1-18 Fig. 15 Interrupt control ............................................................................................................... 1-21 Fig. 16 Structure of interrupt-related registers ......................................................................... 1-21 Fig. 17 Connection example when using key input interrupt and port P8 block diagram 1-22 Fig. 18 Structure of timer related register ................................................................................ 1-23 Fig. 19 Block diagram of timer .................................................................................................. 1-24 Fig. 20 Timing chart of timer 6 PWM1 mode ........................................................................... 1-25 Fig. 21 Block diagram of timer A .............................................................................................. 1-26 Fig. 22 Structure of timer A related registers .......................................................................... 1-26 Fig. 23 Timing chart of timer A PWM, IGBT output modes .................................................. 1-27 Fig. 24 Block diagram of serial I/O ........................................................................................... 1-28 Fig. 25 Structure of serial I/O control register ......................................................................... 1-29 Fig. 26 Serial I/O timing (for LSB first) .................................................................................... 1-29 Fig. 27 Structure of A-D control register .................................................................................. 1-30 Fig. 28 Black diagram of A-D converter ................................................................................... 1-30 Fig. 29 Structure of LCD related registers ............................................................................... 1-31 Fig. 30 Block diagram of LCD controller/driver ....................................................................... 1-32 Fig. 31 Example of circuit at each bias .................................................................................... 1-33 Fig. 32 LCD display RAM map .................................................................................................. 1-34 Fig. 33 LCD drive waveform (1/2 bias) .................................................................................... 1-35 Fig. 34 LCD drive waveform (1/3 bias) .................................................................................... 1-36 Fig. 35 Structure of φ output control register .......................................................................... 1-37 Fig. 36 Structure of ROM correct address register ................................................................. 1-38 Fig. 37 Structure of ROM correct data .................................................................................... 1-38 Fig. 38 Structure of ROM correct enable register 1 ............................................................... 1-38 Fig. 39 Reset circuit example .................................................................................................... 1-39 Fig. 40 Reset sequence .............................................................................................................. 1-39 Fig. 41 Internal status at reset .................................................................................................. 1-40 Fig. 42 Ceramic resonator circuit .............................................................................................. 1-41 Fig. 43 External clock input circuit ............................................................................................ 1-41 Fig. 44 Clock generating circuit block diagram ....................................................................... 1-42 Fig. 45 State transitions of system clock ................................................................................. 1-43 Fig. 46 Programming and testing of One Time PROM version ............................................ 1-45 Fig. 47 Timing chart after interrupt occurs ............................................................................... 1-47 |
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