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M38021E5-XXXSP Datasheet(PDF) 11 Page - Renesas Technology Corp |
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M38021E5-XXXSP Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 208 page ii 3802 GROUP USER’S MANUAL List of figures CHAPTER 2 APPLICATION Fig. 2.1.1 Memory map of I/O port related registers ............................................................... 2-2 Fig. 2.1.2 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6)............................................................... 2-3 Fig. 2.1.3 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6) ................................ 2-3 Fig. 2.2.1 Memory map of timer related registers ......................................................................2-5 Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y .............................................. 2-6 Fig. 2.2.3 Structure of Timer 1 ..................................................................................................... 2-6 Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y .................................................................... 2-7 Fig. 2.2.5 Structure of Timer XY mode register ......................................................................... 2-8 Fig. 2.2.6 Structure of Interrupt request register 1 .................................................................... 2-9 Fig. 2.2.7 Structure of Interrupt request register 2 .................................................................... 2-9 Fig. 2.2.8 Structure of Interrupt control register 1 .................................................................. 2-10 Fig. 2.2.9 Structure of Interrupt control register 2 .................................................................. 2-10 Fig. 2.2.10 Connection of timers and setting of division ratios [Clock function] ................ 2-12 Fig. 2.2.11 Setting of related registers [Clock function] ......................................................... 2-13 Fig. 2.2.12 Control procedure [Clock function] ........................................................................ 2-14 Fig. 2.2.13 Example of a peripheral circuit ...............................................................................2-15 Fig. 2.2.14 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output] ........... 2-15 Fig. 2.2.15 Setting of related registers [Piezoelectric buzzer output] ................................... 2-16 Fig. 2.2.16 Control procedure [Piezoelectric buzzer output] .................................................. 2-16 Fig. 2.2.17 A method for judging if input pulse exists ........................................................... 2-17 Fig. 2.2.18 Setting of related registers [Measurement of frequency] ................................... 2-18 Fig. 2.2.19 Control procedure [Measurement of frequency] ................................................... 2-19 Fig. 2.2.20 Connection of the timer and setting of the division ratio [Measurement of pulse width] ........... 2-20 Fig. 2.2.21 Setting of related registers [Measurement of pulse width] ................................ 2-21 Fig. 2.2.22 Control procedure [Measurement of pulse width] ................................................ 2-22 Fig. 2.3.1 Memory map of serial I/O related registers ........................................................... 2-23 Fig. 2.3.2 Structure of Transmit/Receive buffer register ........................................................ 2-24 Fig. 2.3.3 Structure of Serial I/O1 status register ................................................................... 2-24 Fig. 2.3.4 Structure of Serial I/O1 control register .................................................................. 2-25 Fig. 2.3.5 Structure of UART control register ........................................................................... 2-25 Fig. 2.3.6 Structure of Baud rate generator ..............................................................................2-26 Fig. 2.3.7 Structure of Serial I/O2 control register .................................................................. 2-26 Fig. 2.3.8 Structure of Serial I/O2 register ................................................................................ 2-27 Fig. 2.3.9 Structure of Interrupt edge selection register ........................................................ 2-27 Fig. 2.3.10 Structure of Interrupt request register 1 ............................................................... 2-28 Fig. 2.3.11 Structure of Interrupt request register 2 ............................................................... 2-28 Fig. 2.3.12 Structure of Interrupt control register 1 ................................................................ 2-29 Fig. 2.3.13 Structure of Interrupt control register 2 ................................................................ 2-29 Fig. 2.3.14 Serial I/O connection examples (1) ....................................................................... 2-30 Fig. 2.3.15 Serial I/O connection examples (2) ....................................................................... 2-31 Fig. 2.3.16 Setting of Serial I/O transfer data format ............................................................. 2-32 Fig. 2.3.17 Connection diagram [Communication using a clock synchronous serial I/O] .. 2-33 Fig. 2.3.18 Timing chart [Communication using a clock synchronous serial I/O] ............... 2-33 Fig. 2.3.19 Setting of related registers at a transmitting side [Communication using a clock synchronous serial I/O] ................................ 2-34 Fig. 2.3.20 Setting of related registers at a receiving side [Communication using a clock synchronous serial I/O] ................................ 2-35 |
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