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TMS320TCI6488 Datasheet(PDF) 8 Page - Texas Instruments |
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TMS320TCI6488 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 206 page  2 Device Overview 2.1 Device Characteristics TMS320TCI6487 TMS320TCI6488 Communications Infrastructure Digital Signal Processor SPRS358F – APRIL 2007 – REVISED AUGUST 2008 www.ti.com Table 2-1 provides an overview of the TCI6487/8 DSP. The tables show significant features of the TCI6487/8 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 2-1. Characteristics of the TCI6487/8 Processor HARDWARE FEATURES TCI6487/8 Peripherals DDR2 Memory Controller (32-bit bus width) [1.8 V I/O] 1 Not all peripherals pins (clock memory = DDRREFCLK(N|P) are available at the same EDMA3 (64 independent channels [CPU/3 clock rate] 1 time. High-speed 1x Serial RapidIO Port (2 lanes) 1 (For more detail, see Section 3, Device I2C 1 Configuration) McBSPs 2 (internal or external clock source up to 100 Mbps) 1000 Ethernet MAC (EMAC) 1 Management Data Input/Output (MDIO) 1 Antenna Interface (AIF) 1 Frame Synchronization (FSYNC) 1 64-bit Timers (Configurable) 6 64-bit or 12 32-bit (internal clock source CPU/6 clock frequency) SYSCLKOUT 1 General Purpose Input/Output Port (GPIO) 16 Decoder Coprocessors VCP2 (clock source = CPU/3 clock frequency) 1 TCP2 (clock source = CPU/3 clock frequency) 1 Accelerators Receive Accelerator (RAC) (6488 Only) 1 Rake/Search Accelerator 6 On-Chip Memory Size (Bytes) 3200 KB Organization 32KB L1P Program Cache (SRAM/Cache) 32KB L1D Data Cache (SRAM/Cache) 32KB Data Memory Controller 3072KB Total L2 Unified Memory SRAM/Cache 64KB L3 ROM CPU Megamodule Revision ID Register 0x0 Revision ID (MM_REVID. [15:0]) 0x0181 2000) JTAG Device_ID JTAG Register (address location: 0x0288 0814) Rev. 1.0 JTAG ID = 0x0009 202Fh (VARIANT = 0000b) Rev. 1.1 JTAG ID = 0x1009 202Fh (VARIANT = 0001b) Frequency MHz 1000 (1.0 GHz) Cycle Time ns 1-ns [1.0 GHz CPU] Voltage Core (V) 0.9 V to 1.1 V I/O (V) 1.8 V, 1.1 V PLL1 and PLL1 Controller CLKIN1 Frequency Multiplier Bypass (x1), (x4 to x32) Options PLL2 DDR Clock X10 BGA Package 23 X 23 mm 561-Pin Flip-Chip with BGA CUN/GUN/ZUN Process Technology µm 0.065 µm Device Overview 8 Submit Documentation Feedback |
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