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R5S77641 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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R5S77641 Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 1752 page Rev. 1.00 Nov. 22, 2007 Page xi of lvi 7.2 Register Descriptions ......................................................................................................... 158 7.2.1 Page Table Entry High Register (PTEH) .............................................................. 159 7.2.2 Page Table Entry Low Register (PTEL) ............................................................... 160 7.2.3 Translation Table Base Register (TTB) ................................................................ 161 7.2.4 TLB Exception Address Register (TEA) .............................................................. 162 7.2.5 MMU Control Register (MMUCR) ...................................................................... 162 7.2.6 Page Table Entry Assistance Register (PTEA) ..................................................... 166 7.2.7 Physical Address Space Control Register (PASCR)............................................. 167 7.2.8 Instruction Re-Fetch Inhibit Control Register (IRMCR) ...................................... 168 7.3 TLB Functions (TLB Compatible Mode; MMUCR.ME = 0)............................................ 170 7.3.1 Unified TLB (UTLB) Configuration .................................................................... 170 7.3.2 Instruction TLB (ITLB) Configuration................................................................. 173 7.3.3 Address Translation Method................................................................................. 173 7.4 TLB Functions (TLB Extended Mode; MMUCR.ME = 1) ............................................... 176 7.4.1 Unified TLB (UTLB) Configuration .................................................................... 176 7.4.2 Instruction TLB (ITLB) Configuration................................................................. 179 7.4.3 Address Translation Method................................................................................. 180 7.5 MMU Functions................................................................................................................. 183 7.5.1 MMU Hardware Management .............................................................................. 183 7.5.2 MMU Software Management ............................................................................... 183 7.5.3 MMU Instruction (LDTLB).................................................................................. 184 7.5.4 Hardware ITLB Miss Handling ............................................................................ 186 7.5.5 Avoiding Synonym Problems ............................................................................... 187 7.6 MMU Exceptions............................................................................................................... 189 7.6.1 Instruction TLB Multiple Hit Exception............................................................... 189 7.6.2 Instruction TLB Miss Exception........................................................................... 190 7.6.3 Instruction TLB Protection Violation Exception .................................................. 191 7.6.4 Data TLB Multiple Hit Exception ........................................................................ 192 7.6.5 Data TLB Miss Exception .................................................................................... 192 7.6.6 Data TLB Protection Violation Exception............................................................ 194 7.6.7 Initial Page Write Exception ................................................................................. 195 7.7 Memory-Mapped TLB Configuration................................................................................ 197 7.7.1 ITLB Address Array ............................................................................................. 198 7.7.2 ITLB Data Array (TLB Compatible Mode).......................................................... 199 7.7.3 ITLB Data Array (TLB Extended Mode) ............................................................. 200 7.7.4 UTLB Address Array............................................................................................ 202 7.7.5 UTLB Data Array (TLB Compatible Mode) ........................................................ 203 7.7.6 UTLB Data Array (TLB Extended Mode)............................................................ 204 7.8 Usage Notes ....................................................................................................................... 206 7.8.1 Note on Using LDTLB Instruction ....................................................................... 206 |
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