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R5F21356ADFP Datasheet(PDF) 11 Page - Renesas Technology Corp |
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R5F21356ADFP Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 766 page  A - 4 9.9.1 Stop Mode ......................................................................................................................................... 148 9.9.2 Wait Mode ........................................................................................................................................ 148 9.9.3 Oscillation Stop Detection Function ................................................................................................. 148 9.9.4 Oscillation Circuit Constants ............................................................................................................ 148 10. Protection .................................................................................................................................... 149 10.1 Register .................................................................................................................................................. 149 10.1.1 Protect Register (PRCR) ................................................................................................................... 149 11. Interrupts ..................................................................................................................................... 150 11.1 Overview ............................................................................................................................................... 150 11.1.1 Types of Interrupts ............................................................................................................................ 150 11.1.2 Software Interrupts ........................................................................................................................... 151 11.1.3 Special Interrupts .............................................................................................................................. 152 11.1.4 Peripheral Function Interrupts .......................................................................................................... 152 11.1.5 Interrupts and Interrupt Vectors ........................................................................................................ 153 11.2 Registers ................................................................................................................................................ 155 11.2.1 Interrupt Control Register (TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, S1TIC, S1RIC, TRAIC, TRBIC, U2BCNIC, VCMP1IC, VCMP2IC) .................................................................................................................... 155 11.2.2 Interrupt Control Register (FMRDYIC TRCIC, TRD0IC, TRD1IC, SSUIC/IICIC) ...................... 156 11.2.3 INTi Interrupt Control Register (INTiIC) (i = 0 to 4) ....................................................................... 157 11.3 Interrupt Control .................................................................................................................................... 158 11.3.1 I Flag ................................................................................................................................................. 158 11.3.2 IR Bit ................................................................................................................................................. 158 11.3.3 Bits ILVL2 to ILVL0, IPL ................................................................................................................ 158 11.3.4 Interrupt Sequence ............................................................................................................................ 159 11.3.5 Interrupt Response Time ................................................................................................................... 160 11.3.6 IPL Change when Interrupt Request is Acknowledged .................................................................... 160 11.3.7 Saving Registers ............................................................................................................................... 161 11.3.8 Returning from Interrupt Routine ..................................................................................................... 163 11.3.9 Interrupt Priority ............................................................................................................................... 163 11.3.10 Interrupt Priority Level Selection Circuit ......................................................................................... 164 11.4 INT Interrupt ......................................................................................................................................... 165 11.4.1 INTi Interrupt (i = 0 to 4) .................................................................................................................. 165 11.4.2 INT Interrupt Input Pin Select Register (INTSR) ............................................................................. 165 11.4.3 External Input Enable Register 0 (INTEN) ...................................................................................... 166 11.4.4 External Input Enable Register 1 (INTEN1) .................................................................................... 166 11.4.5 INT Input Filter Select Register 0 (INTF) ........................................................................................ 167 11.4.6 INT Input Filter Select Register 1 (INTF1) ...................................................................................... 167 11.4.7 INTi Input Filter (i = 0 to 4) .............................................................................................................. 168 11.5 Key Input Interrupt ................................................................................................................................ 169 11.5.1 Key Input Enable Register 0 (KIEN) ................................................................................................ 170 11.6 Address Match Interrupt ........................................................................................................................ 171 11.6.1 Address Match Interrupt Enable Register i (AIERi) (i = 0 or 1) ...................................................... 172 11.6.2 Address Match Interrupt Register i (RMADi) (i = 0 or 1) ................................................................ 172 11.7 Timer RC Interrupt, Timer RD Interrupt, Synchronous Serial Communication Unit Interrupt, I2C bus Interface Interrupt, and Flash Memory Interrupt (Interrupts with Multiple Interrupt Request Sources) ................................................................................................................................................................ 173 |
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