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R5F21331ANFP Datasheet(PDF) 9 Page - Renesas Technology Corp |
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R5F21331ANFP Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 617 page A - 2 5.7 Cold Start-Up/Warm Start-Up Determination Function ......................................................................... 36 5.8 Reset Source Determination Function ..................................................................................................... 36 6. Voltage Detection Circuit .............................................................................................................. 37 6.1 Overview ................................................................................................................................................. 37 6.2 Registers .................................................................................................................................................. 41 6.2.1 Voltage Monitor Circuit/Comparator A Control Register (CMPA) ................................................... 41 6.2.2 Voltage Monitor Circuit Edge Select Register (VCAC) .................................................................... 42 6.2.3 Voltage Detect Register (VCA1) ........................................................................................................ 42 6.2.4 Voltage Detect Register 2 (VCA2) ..................................................................................................... 43 6.2.5 Voltage Detection 1 Level Select Register (VD1LS) ......................................................................... 44 6.2.6 Voltage Monitor 0 Circuit Control Register (VW0C) ........................................................................ 45 6.2.7 Voltage Monitor 1 Circuit Control Register (VW1C) ........................................................................ 46 6.2.8 Voltage Monitor 2 Circuit Control Register (VW2C) ........................................................................ 47 6.2.9 Option Function Select Register (OFS) .............................................................................................. 48 6.3 VCC Input Voltage .................................................................................................................................. 49 6.3.1 Monitoring Vdet0 ............................................................................................................................... 49 6.3.2 Monitoring Vdet1 ............................................................................................................................... 49 6.3.3 Monitoring Vdet2 ............................................................................................................................... 49 6.4 Voltage Monitor 0 Reset ......................................................................................................................... 50 6.5 Voltage Monitor 1 Interrupt .................................................................................................................... 51 6.6 Voltage Monitor 2 Interrupt .................................................................................................................... 53 7. I/O Ports ........................................................................................................................................ 55 7.1 Functions of I/O Ports ............................................................................................................................. 55 7.2 Effect on Peripheral Functions ................................................................................................................ 56 7.3 Pins Other than I/O Ports ......................................................................................................................... 56 7.4 Registers .................................................................................................................................................. 68 7.4.1 Port Pi Direction Register (PDi) (i = 0 to 4) ....................................................................................... 68 7.4.2 Port Pi Register (Pi) (i = 0 to 4) .......................................................................................................... 69 7.4.3 Timer RA Pin Select Register (TRASR) ............................................................................................ 70 7.4.4 Timer RB/RC Pin Select Register (TRBRCSR) ................................................................................. 70 7.4.5 Timer RC Pin Select Register 0 (TRCPSR0) ..................................................................................... 71 7.4.6 Timer RC Pin Select Register 1 (TRCPSR1) ..................................................................................... 72 7.4.7 UART0 Pin Select Register (U0SR) ................................................................................................... 73 7.4.8 UART1 Pin Select Register (U1SR) ................................................................................................... 73 7.4.9 UART2 Pin Select Register 0 (U2SR0) .............................................................................................. 74 7.4.10 UART2 Pin Select Register 1 (U2SR1) .............................................................................................. 74 7.4.11 SSU/IIC Pin Select Register (SSUIICSR) .......................................................................................... 75 7.4.12 INT Interrupt Input Pin Select Register (INTSR) ............................................................................... 75 7.4.13 Pull-Up Control Register 0 (PUR0) .................................................................................................... 76 7.4.14 Pull-Up Control Register 1 (PUR1) .................................................................................................... 76 7.4.15 Port P1 Drive Capacity Control Register (P1DRR) ............................................................................ 77 7.4.16 Port P2 Drive Capacity Control Register (P2DRR) ............................................................................ 77 7.4.17 Drive Capacity Control Register 0 (DRR0) ........................................................................................ 78 7.4.18 Drive Capacity Control Register 1 (DRR1) ........................................................................................ 79 7.4.19 Input Threshold Control Register 0 (VLT0) ....................................................................................... 80 7.4.20 Input Threshold Control Register 1 (VLT1) ....................................................................................... 81 7.5 Port Settings ............................................................................................................................................ 82 |
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