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HD6437105 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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HD6437105 Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 560 page  Rev.1.00 Sep. 18, 2008 Page xi of xxxiv REJ09B0069-0100 Section 6 Interrupt Controller (INTC) .............................................................. 73 6.1 Features ............................................................................................................................. 73 6.2 Input/Output Pins .............................................................................................................. 75 6.3 Register Descriptions ........................................................................................................ 75 6.3.1 Interrupt Control Register 1 (ICR1) ..................................................................... 76 6.3.2 Interrupt Control Register 2 (ICR2) ..................................................................... 77 6.3.3 IRQ Status Register (ISR).................................................................................... 79 6.3.4 Interrupt Priority Registers A, D to K (IPRA, IPRD to IPRK) ............................ 80 6.4 Interrupt Sources ............................................................................................................... 82 6.4.1 External Interrupts ............................................................................................... 82 6.4.2 On-Chip Peripheral Module Interrupts ................................................................ 83 6.5 Interrupt Exception Processing Vectors Table.................................................................. 84 6.6 Interrupt Operation............................................................................................................ 87 6.6.1 Interrupt Sequence ............................................................................................... 87 6.6.2 Stack after Interrupt Exception Processing .......................................................... 89 6.7 Interrupt Response Time ................................................................................................... 90 Section 7 Bus State Controller (BSC)............................................................... 93 7.1 Features ............................................................................................................................. 93 7.2 Input/Output Pins .............................................................................................................. 95 7.3 Register Configuration ...................................................................................................... 95 7.4 Address Map ..................................................................................................................... 96 7.5 Register Descriptions ........................................................................................................ 102 7.5.1 Bus Control Register 1 (BCR1) ........................................................................... 102 7.5.2 Bus Control Register 2 (BCR2) ........................................................................... 104 7.5.3 Wait Control Register 1 (WCR1)......................................................................... 105 7.6 Accessing External Space ................................................................................................. 106 7.6.1 Basic Timing........................................................................................................ 106 7.6.2 Wait State Control................................................................................................ 107 7.6.3 CS Assert Period Extension ................................................................................. 109 7.7 Waits between Access Cycles ........................................................................................... 110 7.7.1 Prevention of Data Bus Conflicts......................................................................... 110 7.7.2 Simplification of Bus Cycle Start Detection ........................................................ 110 7.8 Bus Arbitration.................................................................................................................. 111 7.9 Memory Connection Example .......................................................................................... 112 7.10 On-chip Peripheral I/O Register Access ........................................................................... 113 7.11 Cycles in which Bus Is not Released ................................................................................ 113 7.12 CPU Operation when Program Is in External Memory..................................................... 113 |
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