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HD6433641 Datasheet(PDF) 7 Page - Renesas Technology Corp |
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HD6433641 Datasheet(HTML) 7 Page - Renesas Technology Corp |
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7 / 549 page  Rev. 6.00 Sep 12, 2006 page vii of xx Main Revisions in This Edition Item Page Revision (See Manual for Details) All — • Notification of change in company name amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. • Product naming convention amended (Before) H8/3644 Series → (After) H8/3644 Group (Before) H8/3644R Series → (After) H8/3644R Group 3.3.2 Interrupt Control Registers Interrupt Edge Select Register 2 (IEGR2) 64 Description amended IEGR2 is an 8-bit read/write register, used to designate whether pins INT 7 to INT 0, and TMIB are set to rising edge sensing or falling edge sensing. Upon reset, IEGR2 is initialized to H'00. Bit 7 INT 7 Edge Select (INTEG7): Bit 7 selects the input sensing of the INT 7 pin. Bit 7: INTEG7 Description 0 Falling edge of INT7 pin input is detected (initial value) 1 Rising edge of INT7 pin input is detected 6.2.2 Memory Map Table 6.2 Socket Adapter Figure 6.2 Socket Adapter Pin Correspondence (ZTAT) 102, 103 Description of socket adapter deleted 6.8.2 Memory Map Table 6.14 Socket Adapter Product Codes Figure 6.19 Socket Adapter Pin Correspondence (F-ZTAT) 149, 151 Description of socket adapter deleted 6.9 Flash Memory Programming and Erasing Precautions Table 6.18 Flash Memory AC Characteristics 165 Table amended Item Symbol Min Typ Max Unit Test Conditions Flash memory read setup time* 4 tFRS 50 µs VCC ≥ 4.5 V 100 VCC < 4.5 V 8.4.2 Register Configuration and Description Port Mode Register 7 (PMR7) 182 Bit table amended Bit 7 654 321 0 TXD POF1 Initial value 1 1 1 1 1 0 0 0 Read/Write R/W R/W |
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